--- trunk/src/include/cpu_sh.h	2007/10/08 16:20:32	29
+++ trunk/src/include/cpu_sh.h	2007/10/08 16:20:40	30
@@ -28,7 +28,7 @@
  *  SUCH DAMAGE.
  *
  *
- *  $Id: cpu_sh.h,v 1.17 2006/07/16 13:32:28 debug Exp $
+ *  $Id: cpu_sh.h,v 1.21 2006/07/25 21:49:14 debug Exp $
  */
 
 #include "misc.h"
@@ -36,10 +36,27 @@
 
 struct cpu_family;
 
+/*  SH CPU types:  */
+struct sh_cpu_type_def {
+	char		*name;
+	int		bits;
+};
+
+#define	SH_CPU_TYPE_DEFS	{	\
+	{ "SH3", 32 },			\
+	{ "SH4", 32 },			\
+	{ "SH5", 64 },			\
+	{ NULL, 0 } }
+
 
-#define	SH_N_IC_ARGS			3
-#define	SH_INSTR_ALIGNMENT_SHIFT	2
-#define	SH_IC_ENTRIES_SHIFT		10
+/*
+ *  TODO: Figure out how to nicely support multiple instruction encodings!
+ *  For now, I'm reverting this to SH4. SH5 will have to wait until later.
+ */
+
+#define	SH_N_IC_ARGS			2	/*  3 for SH5/SH64  */
+#define	SH_INSTR_ALIGNMENT_SHIFT	1	/*  2 for SH5/SH64  */
+#define	SH_IC_ENTRIES_SHIFT		11	/*  10 for SH5/SH64  */
 #define	SH_IC_ENTRIES_PER_PAGE		(1 << SH_IC_ENTRIES_SHIFT)
 #define	SH_PC_TO_IC_ENTRY(a)		(((a)>>SH_INSTR_ALIGNMENT_SHIFT) \
 					& (SH_IC_ENTRIES_PER_PAGE-1))
@@ -55,11 +72,31 @@
 #define	SH_MAX_VPH_TLB_ENTRIES		128
 
 
+#define	SH_N_GPRS		64
+
+
 struct sh_cpu {
-	int		bits;
+	struct sh_cpu_type_def cpu_type;
+
+	/*  compact = 1 if currently executing 16-bit long opcodes  */
 	int		compact;
 
-	uint64_t	r[64];
+	uint32_t	r_otherbank[8];
+
+	uint64_t	r[SH_N_GPRS];
+
+	uint32_t	mach;		/*  Multiply-Accumulate High  */
+	uint32_t	macl;		/*  Multiply-Accumulate Low  */
+	uint32_t	pr;		/*  Procedure Register  */
+	uint32_t	fpscr;		/*  Floating-point Status/Control  */
+	uint32_t	fpul;		/*  Floating-point Communication Reg  */
+	uint32_t	sr;		/*  Status Register  */
+	uint32_t	ssr;		/*  Saved Status Register  */
+	uint32_t	spc;		/*  Saved PC  */
+	uint32_t	gbr;		/*  Global Base Register  */
+	uint32_t	vbr;		/*  Vector Base Register  */
+	uint32_t	sgr;		/*  Saved General Register  */
+	uint32_t	dbr;		/*  Debug Base Register  */
 
 
 	/*
@@ -73,6 +110,19 @@
 };
 
 
+/*  Status register bits:  */
+#define	SH_SR_T			0x00000001	/*  True/false  */
+#define	SH_SR_S			0x00000002	/*  Saturation  */
+#define	SH_SR_IMASK		0x000000f0	/*  Interrupt mask  */
+#define	SH_SR_IMASK_SHIFT		4
+#define	SH_SR_Q			0x00000100	/*  State for Divide Step  */
+#define	SH_SR_M			0x00000200	/*  State for Divide Step  */
+#define	SH_SR_FD		0x00008000	/*  FPU Disable  */
+#define	SH_SR_BL		0x10000000	/*  Exception/Interrupt Block */
+#define	SH_SR_RB		0x20000000	/*  Register Bank 0/1  */
+#define	SH_SR_MD		0x40000000	/*  Privileged Mode  */
+
+
 /*  cpu_sh.c:  */
 int sh_run_instr(struct cpu *cpu);
 void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
@@ -89,5 +139,11 @@
 	unsigned char *data, size_t len, int writeflag, int cache_flags);
 int sh_cpu_family_init(struct cpu_family *);
 
+void sh_update_sr(struct cpu *cpu, uint32_t new_sr);
+
+/*  memory_sh.c:  */
+int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr,
+	uint64_t *return_addr, int flags);
+
 
 #endif	/*  CPU_SH_H  */