/[gxemul]/trunk/src/include/cpu_sh.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 41 by dpavlin, Mon Oct 8 16:22:11 2007 UTC revision 42 by dpavlin, Mon Oct 8 16:22:32 2007 UTC
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_sh.h,v 1.41 2007/04/28 09:19:34 debug Exp $   *  $Id: cpu_sh.h,v 1.46 2007/06/07 15:36:25 debug Exp $
32   *   *
33   *  Note: Many things here are SH4-specific, so it probably doesn't work   *  Note: Many things here are SH4-specific, so it probably doesn't work
34   *        for SH3 emulation.   *        for SH3 emulation.
# Line 40  Line 40 
40    
41    
42  struct cpu_family;  struct cpu_family;
43    struct timer;
44    
45    
46  /*  SH CPU types:  */  /*  SH CPU types:  */
47  struct sh_cpu_type_def {  struct sh_cpu_type_def {
# Line 51  struct sh_cpu_type_def { Line 53  struct sh_cpu_type_def {
53  };  };
54    
55  #define SH_CPU_TYPE_DEFS                                {           \  #define SH_CPU_TYPE_DEFS                                {           \
56            { "SH7708R", 32, 3, 0,              0,                   }, \
57          { "SH7750",  32, 4, SH4_PVR_SH7750, 0                    }, \          { "SH7750",  32, 4, SH4_PVR_SH7750, 0                    }, \
58          { "SH7750R", 32, 4, SH4_PVR_SH7750, SH4_PRR_7750R        }, \          { "SH7750R", 32, 4, SH4_PVR_SH7750, SH4_PRR_7750R        }, \
59          { "SH7751R", 32, 4, SH4_PVR_SH7751, SH4_PRR_7751R        }, \          { "SH7751R", 32, 4, SH4_PVR_SH7751, SH4_PRR_7751R        }, \
60          { "SH5",     64, 5, 0,              0                    }, \          /* { "SH5",  64, 5, 0,              0                    }, */ \
61          { NULL,       0, 0, 0,              0                    }  }          { NULL,       0, 0, 0,              0                    }  }
62    
63    
# Line 90  DYNTRANS_MISC_DECLARATIONS(sh,SH,uint32_ Line 93  DYNTRANS_MISC_DECLARATIONS(sh,SH,uint32_
93  struct sh_cpu {  struct sh_cpu {
94          struct sh_cpu_type_def cpu_type;          struct sh_cpu_type_def cpu_type;
95    
         /*  compact = 1 if currently executing 16-bit long opcodes  */  
         int             compact;  
   
96          /*  General Purpose Registers:  */          /*  General Purpose Registers:  */
97          uint32_t        r[SH_N_GPRS];          uint32_t        r[SH_N_GPRS];
98          uint32_t        r_bank[SH_N_GPRS_BANKED];          uint32_t        r_bank[SH_N_GPRS_BANKED];
# Line 173  struct sh_cpu { Line 173  struct sh_cpu {
173           */           */
174          DYNTRANS_ITC(sh)          DYNTRANS_ITC(sh)
175          VPH_TLBS(sh,SH)          VPH_TLBS(sh,SH)
176          VPH32(sh,SH,uint32_t,uint8_t)          VPH32(sh,SH)
177  };  };
178    
179    
# Line 234  void sh32_update_translation_table(struc Line 234  void sh32_update_translation_table(struc
234  void sh32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);  void sh32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
235  void sh32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);  void sh32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
236  void sh_init_64bit_dummy_tables(struct cpu *cpu);  void sh_init_64bit_dummy_tables(struct cpu *cpu);
237    void sh_timer_sample_tick(struct timer *, void *);
238  int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,  int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
239          unsigned char *data, size_t len, int writeflag, int cache_flags);          unsigned char *data, size_t len, int writeflag, int cache_flags);
240  int sh_cpu_family_init(struct cpu_family *);  int sh_cpu_family_init(struct cpu_family *);
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