src/include/cpu_sh.h

#ifndef CPU_SH_H
#define CPU_SH_H

/*
 *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_sh.h,v 1.37 2006/12/30 13:31:00 debug Exp $
 *
 *  Note: Many things here are SH4-specific, so it probably doesn't work
 *        for SH3 emulation.
 */

#include "interrupt.h"
#include "misc.h"
#include "sh4_cpu.h"


struct cpu_family;

/*  SH CPU types:  */
struct sh_cpu_type_def {
        char            *name;
        int             bits;
        int             arch;
        uint32_t        pvr;
        uint32_t        prr;
};

#define SH_CPU_TYPE_DEFS                {           \
        { "SH7750", 32, 4, SH4_PVR_SH7750, 0     }, \
        { "SH5",    64, 5, 0,              0     }, \
        { NULL,      0, 0, 0,              0     }  }


/*
 *  TODO: Figure out how to nicely support multiple instruction encodings!
 *  For now, I'm reverting this to SH4. SH5 will have to wait until later.
 */

#define SH_N_IC_ARGS                    2       /*  3 for SH5/SH64  */
#define SH_INSTR_ALIGNMENT_SHIFT        1       /*  2 for SH5/SH64  */
#define SH_IC_ENTRIES_SHIFT             11      /*  10 for SH5/SH64  */
#define SH_IC_ENTRIES_PER_PAGE          (1 << SH_IC_ENTRIES_SHIFT)
#define SH_PC_TO_IC_ENTRY(a)            (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \
                                        & (SH_IC_ENTRIES_PER_PAGE-1))
#define SH_ADDR_TO_PAGENR(a)            ((a) >> (SH_IC_ENTRIES_SHIFT \
                                        + SH_INSTR_ALIGNMENT_SHIFT))

DYNTRANS_MISC_DECLARATIONS(sh,SH,uint32_t)

#define SH_MAX_VPH_TLB_ENTRIES          128


#define SH_N_GPRS               16
#define SH_N_GPRS_BANKED        8
#define SH_N_FPRS               16

#define SH_N_ITLB_ENTRIES       4
#define SH_N_UTLB_ENTRIES       64

#define SH_INVALID_INSTR        0x00fb


struct sh_cpu {
        struct sh_cpu_type_def cpu_type;

        /*  compact = 1 if currently executing 16-bit long opcodes  */
        int             compact;

        /*  General Purpose Registers:  */
        uint32_t        r[SH_N_GPRS];
        uint32_t        r_bank[SH_N_GPRS_BANKED];

        /*  Floating-Point Registers:  */
        uint32_t        fr[SH_N_FPRS];
        uint32_t        xf[SH_N_FPRS];  /*  "Other bank."  */

        uint32_t        mach;           /*  Multiply-Accumulate High  */
        uint32_t        macl;           /*  Multiply-Accumulate Low  */
        uint32_t        pr;             /*  Procedure Register  */
        uint32_t        fpscr;          /*  Floating-point Status/Control  */
        uint32_t        fpul;           /*  Floating-point Communication Reg  */
        uint32_t        sr;             /*  Status Register  */
        uint32_t        ssr;            /*  Saved Status Register  */
        uint32_t        spc;            /*  Saved PC  */
        uint32_t        gbr;            /*  Global Base Register  */
        uint32_t        vbr;            /*  Vector Base Register  */
        uint32_t        sgr;            /*  Saved General Register  */
        uint32_t        dbr;            /*  Debug Base Register  */

        /*  Cache control:  */
        uint32_t        ccr;            /*  Cache Control Register  */
        uint32_t        qacr0;          /*  Queue Address Control Register 0  */
        uint32_t        qacr1;          /*  Queue Address Control Register 1  */

        /*  MMU/TLB registers:  */
        uint32_t        pteh;           /*  Page Table Entry High  */
        uint32_t        ptel;           /*  Page Table Entry Low  */
        uint32_t        ptea;           /*  Page Table Entry A  */
        uint32_t        ttb;            /*  Translation Table Base  */
        uint32_t        tea;            /*  TLB Exception Address Register  */
        uint32_t        mmucr;          /*  MMU Control Register  */
        uint32_t        itlb_hi[SH_N_ITLB_ENTRIES];
        uint32_t        itlb_lo[SH_N_ITLB_ENTRIES];
        uint32_t        utlb_hi[SH_N_UTLB_ENTRIES];
        uint32_t        utlb_lo[SH_N_UTLB_ENTRIES];

        /*  Exception handling:  */
        uint32_t        tra;            /*  TRAPA Exception Register  */
        uint32_t        expevt;         /*  Exception Event Register  */
        uint32_t        intevt;         /*  Interrupt Event Register  */

        /*  Interrupt controller:  */
        uint16_t        intc_ipra;      /*  Interrupt Priority Registers  */
        uint16_t        intc_iprb;
        uint16_t        intc_iprc;
        uint16_t        intc_iprd;
        int16_t         int_to_assert;  /*  Calculated int to assert  */
        int             int_level;      /*  Calculated int level  */
        uint32_t        int_pending[0x1000 / 0x20 / (sizeof(uint32_t)*8)];

        /*  Timer/clock functionality:  */
        int             pclock;

        /*  DMA Controller: (4 channels)  */
        uint32_t        dmac_sar[4];
        uint32_t        dmac_dar[4];
        uint32_t        dmac_tcr[4];
        uint32_t        dmac_chcr[4];


        /*
         *  Instruction translation cache and Virtual->Physical->Host
         *  address translation:
         */
        DYNTRANS_ITC(sh)
        VPH_TLBS(sh,SH)
        VPH32(sh,SH,uint64_t,uint8_t)
};


/*  Status register bits:  */
#define SH_SR_T                 0x00000001      /*  True/false  */
#define SH_SR_S                 0x00000002      /*  Saturation  */
#define SH_SR_IMASK             0x000000f0      /*  Interrupt mask  */
#define SH_SR_IMASK_SHIFT               4
#define SH_SR_Q                 0x00000100      /*  State for Divide Step  */
#define SH_SR_M                 0x00000200      /*  State for Divide Step  */
#define SH_SR_FD                0x00008000      /*  FPU Disable  */
#define SH_SR_BL                0x10000000      /*  Exception/Interrupt Block */
#define SH_SR_RB                0x20000000      /*  Register Bank 0/1  */
#define SH_SR_MD                0x40000000      /*  Privileged Mode  */

/*  Floating-point status/control register bits:  */
#define SH_FPSCR_RM_MASK        0x00000003      /*  Rounding Mode  */
#define    SH_FPSCR_RM_NEAREST         0x0      /*  Round to nearest  */
#define    SH_FPSCR_RM_ZERO            0x1      /*  Round to zero  */
#define SH_FPSCR_INEXACT        0x00000004      /*  Inexact exception  */
#define SH_FPSCR_UNDERFLOW      0x00000008      /*  Underflow exception  */
#define SH_FPSCR_OVERFLOW       0x00000010      /*  Overflow exception  */
#define SH_FPSCR_DIV_BY_ZERO    0x00000020      /*  Div by zero exception  */
#define SH_FPSCR_INVALID        0x00000040      /*  Invalid exception  */
#define SH_FPSCR_EN_INEXACT     0x00000080      /*  Inexact enable  */
#define SH_FPSCR_EN_UNDERFLOW   0x00000100      /*  Underflow enable  */
#define SH_FPSCR_EN_OVERFLOW    0x00000200      /*  Overflow enable  */
#define SH_FPSCR_EN_DIV_BY_ZERO 0x00000400      /*  Div by zero enable  */
#define SH_FPSCR_EN_INVALID     0x00000800      /*  Invalid enable  */
#define SH_FPSCR_CAUSE_INEXACT  0x00001000      /*  Cause Inexact  */
#define SH_FPSCR_CAUSE_UNDERFLOW 0x00002000     /*  Cause Underflow  */
#define SH_FPSCR_CAUSE_OVERFLOW 0x00004000      /*  Cause Overflow  */
#define SH_FPSCR_CAUSE_DIVBY0   0x00008000      /*  Cause Div by 0  */
#define SH_FPSCR_CAUSE_INVALID  0x00010000      /*  Cause Invalid  */
#define SH_FPSCR_CAUSE_ERROR    0x00020000      /*  Cause Error  */
#define SH_FPSCR_DN_ZERO        0x00040000      /*  Denormalization Mode  */
#define SH_FPSCR_PR             0x00080000      /*  Double-Precision Mode  */
#define SH_FPSCR_SZ             0x00100000      /*  Double-Precision Size  */
#define SH_FPSCR_FR             0x00200000      /*  Register Bank Select  */


/*  cpu_sh.c:  */
void sh_cpu_interrupt_assert(struct interrupt *interrupt);
void sh_cpu_interrupt_deassert(struct interrupt *interrupt);
int sh_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
int sh_run_instr(struct cpu *cpu);
void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void sh_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
int sh32_run_instr(struct cpu *cpu);
void sh32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void sh32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
void sh32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
void sh_init_64bit_dummy_tables(struct cpu *cpu);
int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
        unsigned char *data, size_t len, int writeflag, int cache_flags);
int sh_cpu_family_init(struct cpu_family *);

void sh_update_sr(struct cpu *cpu, uint32_t new_sr);
void sh_exception(struct cpu *cpu, int expevt, int intevt, uint32_t vaddr);

/*  memory_sh.c:  */
int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr,
        uint64_t *return_addr, int flags);


#endif  /*  CPU_SH_H  */
1	dpavlin	14	#ifndef CPU_SH_H
2			#define CPU_SH_H
3
4			/*
5	dpavlin	34	* Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
6	dpavlin	14	*
7			* Redistribution and use in source and binary forms, with or without
8			* modification, are permitted provided that the following conditions are met:
9			*
10			* 1. Redistributions of source code must retain the above copyright
11			* notice, this list of conditions and the following disclaimer.
12			* 2. Redistributions in binary form must reproduce the above copyright
13			* notice, this list of conditions and the following disclaimer in the
14			* documentation and/or other materials provided with the distribution.
15			* 3. The name of the author may not be used to endorse or promote products
16			* derived from this software without specific prior written permission.
17			*
18			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28			* SUCH DAMAGE.
29			*
30			*
31	dpavlin	34	* $Id: cpu_sh.h,v 1.37 2006/12/30 13:31:00 debug Exp $
32	dpavlin	32	*
33			* Note: Many things here are SH4-specific, so it probably doesn't work
34			* for SH3 emulation.
35	dpavlin	14	*/
36
37	dpavlin	34	#include "interrupt.h"
38	dpavlin	14	#include "misc.h"
39	dpavlin	32	#include "sh4_cpu.h"
40	dpavlin	14
41
42			struct cpu_family;
43
44	dpavlin	30	/* SH CPU types: */
45			struct sh_cpu_type_def {
46			char *name;
47			int bits;
48	dpavlin	32	int arch;
49			uint32_t pvr;
50			uint32_t prr;
51	dpavlin	30	};
52	dpavlin	14
53	dpavlin	32	#define SH_CPU_TYPE_DEFS { \
54			{ "SH7750", 32, 4, SH4_PVR_SH7750, 0 }, \
55			{ "SH5", 64, 5, 0, 0 }, \
56			{ NULL, 0, 0, 0, 0 } }
57	dpavlin	30
58
59			/*
60			* TODO: Figure out how to nicely support multiple instruction encodings!
61			* For now, I'm reverting this to SH4. SH5 will have to wait until later.
62			*/
63
64			#define SH_N_IC_ARGS 2 /* 3 for SH5/SH64 */
65			#define SH_INSTR_ALIGNMENT_SHIFT 1 /* 2 for SH5/SH64 */
66			#define SH_IC_ENTRIES_SHIFT 11 /* 10 for SH5/SH64 */
67	dpavlin	14	#define SH_IC_ENTRIES_PER_PAGE (1 << SH_IC_ENTRIES_SHIFT)
68			#define SH_PC_TO_IC_ENTRY(a) (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \
69			& (SH_IC_ENTRIES_PER_PAGE-1))
70			#define SH_ADDR_TO_PAGENR(a) ((a) >> (SH_IC_ENTRIES_SHIFT \
71			+ SH_INSTR_ALIGNMENT_SHIFT))
72
73	dpavlin	32	DYNTRANS_MISC_DECLARATIONS(sh,SH,uint32_t)
74	dpavlin	24
75	dpavlin	22	#define SH_MAX_VPH_TLB_ENTRIES 128
76	dpavlin	14
77
78	dpavlin	32	#define SH_N_GPRS 16
79			#define SH_N_GPRS_BANKED 8
80			#define SH_N_FPRS 16
81	dpavlin	30
82	dpavlin	32	#define SH_N_ITLB_ENTRIES 4
83			#define SH_N_UTLB_ENTRIES 64
84	dpavlin	30
85	dpavlin	34	#define SH_INVALID_INSTR 0x00fb
86	dpavlin	32
87	dpavlin	34
88	dpavlin	14	struct sh_cpu {
89	dpavlin	30	struct sh_cpu_type_def cpu_type;
90
91			/* compact = 1 if currently executing 16-bit long opcodes */
92	dpavlin	14	int compact;
93
94	dpavlin	32	/* General Purpose Registers: */
95			uint32_t r[SH_N_GPRS];
96			uint32_t r_bank[SH_N_GPRS_BANKED];
97	dpavlin	14
98	dpavlin	32	/* Floating-Point Registers: */
99			uint32_t fr[SH_N_FPRS];
100			uint32_t xf[SH_N_FPRS]; /* "Other bank." */
101	dpavlin	14
102	dpavlin	30	uint32_t mach; /* Multiply-Accumulate High */
103			uint32_t macl; /* Multiply-Accumulate Low */
104			uint32_t pr; /* Procedure Register */
105			uint32_t fpscr; /* Floating-point Status/Control */
106			uint32_t fpul; /* Floating-point Communication Reg */
107			uint32_t sr; /* Status Register */
108			uint32_t ssr; /* Saved Status Register */
109			uint32_t spc; /* Saved PC */
110			uint32_t gbr; /* Global Base Register */
111			uint32_t vbr; /* Vector Base Register */
112			uint32_t sgr; /* Saved General Register */
113			uint32_t dbr; /* Debug Base Register */
114
115	dpavlin	32	/* Cache control: */
116			uint32_t ccr; /* Cache Control Register */
117			uint32_t qacr0; /* Queue Address Control Register 0 */
118			uint32_t qacr1; /* Queue Address Control Register 1 */
119	dpavlin	30
120	dpavlin	32	/* MMU/TLB registers: */
121			uint32_t pteh; /* Page Table Entry High */
122			uint32_t ptel; /* Page Table Entry Low */
123			uint32_t ptea; /* Page Table Entry A */
124			uint32_t ttb; /* Translation Table Base */
125			uint32_t tea; /* TLB Exception Address Register */
126			uint32_t mmucr; /* MMU Control Register */
127			uint32_t itlb_hi[SH_N_ITLB_ENTRIES];
128			uint32_t itlb_lo[SH_N_ITLB_ENTRIES];
129			uint32_t utlb_hi[SH_N_UTLB_ENTRIES];
130			uint32_t utlb_lo[SH_N_UTLB_ENTRIES];
131
132			/* Exception handling: */
133			uint32_t tra; /* TRAPA Exception Register */
134			uint32_t expevt; /* Exception Event Register */
135			uint32_t intevt; /* Interrupt Event Register */
136
137			/* Interrupt controller: */
138			uint16_t intc_ipra; /* Interrupt Priority Registers */
139			uint16_t intc_iprb;
140			uint16_t intc_iprc;
141	dpavlin	34	uint16_t intc_iprd;
142	dpavlin	32	int16_t int_to_assert; /* Calculated int to assert */
143			int int_level; /* Calculated int level */
144			uint32_t int_pending[0x1000 / 0x20 / (sizeof(uint32_t)*8)];
145
146			/* Timer/clock functionality: */
147			int pclock;
148
149	dpavlin	34	/* DMA Controller: (4 channels) */
150			uint32_t dmac_sar[4];
151			uint32_t dmac_dar[4];
152			uint32_t dmac_tcr[4];
153			uint32_t dmac_chcr[4];
154	dpavlin	32
155	dpavlin	34
156	dpavlin	14	/*
157	dpavlin	22	* Instruction translation cache and Virtual->Physical->Host
158			* address translation:
159	dpavlin	14	*/
160	dpavlin	22	DYNTRANS_ITC(sh)
161			VPH_TLBS(sh,SH)
162			VPH32(sh,SH,uint64_t,uint8_t)
163	dpavlin	14	};
164
165
166	dpavlin	30	/* Status register bits: */
167			#define SH_SR_T 0x00000001 /* True/false */
168			#define SH_SR_S 0x00000002 /* Saturation */
169			#define SH_SR_IMASK 0x000000f0 /* Interrupt mask */
170			#define SH_SR_IMASK_SHIFT 4
171			#define SH_SR_Q 0x00000100 /* State for Divide Step */
172			#define SH_SR_M 0x00000200 /* State for Divide Step */
173			#define SH_SR_FD 0x00008000 /* FPU Disable */
174			#define SH_SR_BL 0x10000000 /* Exception/Interrupt Block */
175			#define SH_SR_RB 0x20000000 /* Register Bank 0/1 */
176			#define SH_SR_MD 0x40000000 /* Privileged Mode */
177
178	dpavlin	32	/* Floating-point status/control register bits: */
179			#define SH_FPSCR_RM_MASK 0x00000003 /* Rounding Mode */
180			#define SH_FPSCR_RM_NEAREST 0x0 /* Round to nearest */
181			#define SH_FPSCR_RM_ZERO 0x1 /* Round to zero */
182			#define SH_FPSCR_INEXACT 0x00000004 /* Inexact exception */
183			#define SH_FPSCR_UNDERFLOW 0x00000008 /* Underflow exception */
184			#define SH_FPSCR_OVERFLOW 0x00000010 /* Overflow exception */
185			#define SH_FPSCR_DIV_BY_ZERO 0x00000020 /* Div by zero exception */
186			#define SH_FPSCR_INVALID 0x00000040 /* Invalid exception */
187			#define SH_FPSCR_EN_INEXACT 0x00000080 /* Inexact enable */
188			#define SH_FPSCR_EN_UNDERFLOW 0x00000100 /* Underflow enable */
189			#define SH_FPSCR_EN_OVERFLOW 0x00000200 /* Overflow enable */
190			#define SH_FPSCR_EN_DIV_BY_ZERO 0x00000400 /* Div by zero enable */
191			#define SH_FPSCR_EN_INVALID 0x00000800 /* Invalid enable */
192			#define SH_FPSCR_CAUSE_INEXACT 0x00001000 /* Cause Inexact */
193			#define SH_FPSCR_CAUSE_UNDERFLOW 0x00002000 /* Cause Underflow */
194			#define SH_FPSCR_CAUSE_OVERFLOW 0x00004000 /* Cause Overflow */
195			#define SH_FPSCR_CAUSE_DIVBY0 0x00008000 /* Cause Div by 0 */
196			#define SH_FPSCR_CAUSE_INVALID 0x00010000 /* Cause Invalid */
197			#define SH_FPSCR_CAUSE_ERROR 0x00020000 /* Cause Error */
198			#define SH_FPSCR_DN_ZERO 0x00040000 /* Denormalization Mode */
199			#define SH_FPSCR_PR 0x00080000 /* Double-Precision Mode */
200			#define SH_FPSCR_SZ 0x00100000 /* Double-Precision Size */
201			#define SH_FPSCR_FR 0x00200000 /* Register Bank Select */
202	dpavlin	30
203	dpavlin	32
204	dpavlin	14	/* cpu_sh.c: */
205	dpavlin	34	void sh_cpu_interrupt_assert(struct interrupt *interrupt);
206			void sh_cpu_interrupt_deassert(struct interrupt *interrupt);
207	dpavlin	32	int sh_cpu_instruction_has_delayslot(struct cpu cpu, unsigned char ib);
208	dpavlin	28	int sh_run_instr(struct cpu *cpu);
209	dpavlin	14	void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
210			unsigned char *host_page, int writeflag, uint64_t paddr_page);
211	dpavlin	18	void sh_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
212	dpavlin	14	void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
213	dpavlin	28	int sh32_run_instr(struct cpu *cpu);
214	dpavlin	14	void sh32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
215			unsigned char *host_page, int writeflag, uint64_t paddr_page);
216	dpavlin	18	void sh32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
217	dpavlin	14	void sh32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
218	dpavlin	24	void sh_init_64bit_dummy_tables(struct cpu *cpu);
219	dpavlin	14	int sh_memory_rw(struct cpu cpu, struct memory mem, uint64_t vaddr,
220			unsigned char *data, size_t len, int writeflag, int cache_flags);
221			int sh_cpu_family_init(struct cpu_family *);
222
223	dpavlin	30	void sh_update_sr(struct cpu *cpu, uint32_t new_sr);
224	dpavlin	32	void sh_exception(struct cpu *cpu, int expevt, int intevt, uint32_t vaddr);
225	dpavlin	14
226	dpavlin	30	/* memory_sh.c: */
227			int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr,
228			uint64_t *return_addr, int flags);
229
230
231	dpavlin	14	#endif /* CPU_SH_H */