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Revision Log
++ trunk/HISTORY (local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816 Adding a framework for emulated/virtual timers (src/timer.c),
using only setitimer().
Rewriting the mc146818 to use the new timer framework.
20060817 Adding a call to gettimeofday() every now and then (once every
second, at the moment) to resynch the timer if it drifts.
Beginning to convert the ISA timer interrupt mechanism (8253
and 8259) to use the new timer framework.
Removing the -I command line option.
20060819 Adding the -I command line option again, with new semantics.
Working on Footbridge timer interrupts; NetBSD/NetWinder and
NetBSD/CATS now run at correct speed, but unfortunately with
HUGE delays during bootup.
20060821 Some minor m68k updates. Adding the first instruction: nop. :)
Minor Alpha emulation updates.
20060822 Adding a FreeBSD development specific YAMON environment
variable ("khz") (as suggested by Bruce M. Simpson).
Moving YAMON environment variable initialization from
machine_evbmips.c into promemul/yamon.c, and adding some more
variables.
Continuing on the LCA PCI bus controller (for Alpha machines).
20060823 Continuing on the timer stuff: experimenting with MIPS count/
compare interrupts connected to the timer framework.
20060825 Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
Minor updates to the LCA PCI controller.
20060827 Implementing a CHIP8 cpu mode, and a corresponding CHIP8
machine, for fun. Disassembly support for all instructions,
and most of the common instructions have been implemented: mvi,
mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828 Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
(more correct) RCA 180x cpu. (Disassembly for all 1802
instructions has been implemented, but no execution yet, and
no 1805 extended instructions.)
20060829 Minor Alpha emulation updates.
20060830 Beginning to experiment a little with PCI IDE for SGI O2.
Fixing the cursor key mappings for MobilePro 770 emulation.
Fixing the LK201 warning caused by recent NetBSD/pmax.
The MIPS R41xx standby, suspend, and hibernate instructions now
behave like the RM52xx/MIPS32/MIPS64 wait instruction.
Fixing dev_wdc so it calculates correct (64-bit) offsets before
giving them to diskimage_access().
20060831 Continuing on Alpha emulation (OSF1 PALcode).
20060901 Minor Alpha updates; beginning on virtual memory pagetables.
Removed the limit for max nr of devices (in preparation for
allowing devices' base addresses to be changed during runtime).
Adding a hack for MIPS [d]mfc0 select 0 (except the count
register), so that the coproc register is simply copied.
The MIPS suspend instruction now exits the emulator, instead
of being treated as a wait instruction (this causes NetBSD/
hpcmips to get correct 'halt' behavior).
The VR41xx RTC now returns correct time.
Connecting the VR41xx timer to the timer framework (fixed at
128 Hz, for now).
Continuing on SPARC emulation, adding more instructions:
restore, ba_xcc, ble. The rectangle drawing demo works :)
Removing the last traces of the old ENABLE_CACHE_EMULATION
MIPS stuff (not usable with dyntrans anyway).
20060902 Splitting up src/net.c into several smaller files in its own
subdirectory (src/net/).
20060903 Cleanup of the files in src/net/, to make them less ugly.
20060904 Continuing on the 'settings' subsystem.
Minor progress on the SPARC emulation mode.
20060905 Cleanup of various things, and connecting the settings
infrastructure to various subsystems (emul, machine, cpu, etc).
Changing the lk201 mouse update routine to not rely on any
emulated hardware framebuffer cursor coordinates, but instead
always do (semi-usable) relative movements.
20060906 Continuing on the lk201 mouse stuff. Mouse behaviour with
multiple framebuffers (which was working in Ultrix) is now
semi-broken (but it still works, in a way).
Moving the documentation about networking into its own file
(networking.html), and refreshing it a bit. Adding an example
of how to use ethernet frame direct-access (udp_snoop).
20060907 Continuing on the settings infrastructure.
20060908 Minor updates to SH emulation: for 32-bit emulation: delay
slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
ice, for now.
20060909-10 Implementing some more 32-bit SH instructions. Removing the
64-bit mode completely. Enough has now been implemented to run
the rectangle drawing demo. :-)
20060912 Adding more SH instructions.
20060916 Continuing on SH emulation (some more instructions: div0u,
div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
Continuing on the settings subsystem (beginning on reading/
writing settings, removing bugs, and connecting more cpus to
the framework).
20060919 More work on SH emulation; adding an ldc banked instruction,
and attaching a 640x480 framebuffer to the Dreamcast machine
mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
and then panics).
20060920 Continuing on the settings subsystem.
20060921 Fixing the Footbridge timer stuff so that NetBSD/cats and
NetBSD/netwinder boot up without the delays.
20060922 Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
'wait' support disabled, NetBSD/malta and Linux/malta run at
correct speed.
20060923 Connecting dev_gt to the timer framework, so that NetBSD/cobalt
runs at correct speed.
Moving SH4-specific memory mapped registers into its own
device (dev_sh4.c).
Running with -N now prints "idling" instead of bogus nr of
instrs/second (which isn't valid anyway) while idling.
20060924 Algor emulation should now run at correct speed.
Adding disassembly support for some MIPS64 revision 2
instructions: ext, dext, dextm, dextu.
20060926 The timer framework now works also when the MIPS wait
instruction is used.
20060928 Re-implementing checks for coprocessor availability for MIPS
cop0 instructions. (Thanks to Carl van Schaik for noticing the
lack of cop0 availability checks.)
20060929 Implementing an instruction combination hack which treats
NetBSD/pmax' idle loop as a wait-like instruction.
20060930 The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
causing TLB lookups to sometimes succeed when they should have
failed. (A big thank you to Juli Mallett for noticing the
problem.)
Adding disassembly support for more MIPS64 revision 2 opcodes
(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
implementing seb, seh, dsbh, dshd, and wsbh.
Implementing an instruction combination hack for Linux/pmax'
idle loop, similar to the NetBSD/pmax case.
20061001 Changing the NetBSD/sgimips install instructions to extract
files from an iso image, instead of downloading them via ftp.
20061002 More-than-31-bit userland addresses in memory_mips_v2p.c were
not actually working; applying a fix from Carl van Schaik to
enable them to work + making some other updates (adding kuseg
support).
Fixing hpcmips (vr41xx) timer initialization.
Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
loop. Seems to work both for R3000 and non-R3000.
20061003 Continuing a little on SH emulation (adding more control
registers; mini-cleanup of memory_sh.c).
20061004 Beginning on a dev_rtc, a clock/timer device for the test
machines; also adding a demo, and some documentation.
Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
sign-extended), and adding the addc and ldtlb instructions.
20061005 Contining on SH emulation: virtual to physical address
translation, and a skeleton exception mechanism.
20061006 Adding more SH instructions (various loads and stores, rte,
negc, muls.w, various privileged register-move instructions).
20061007 More SH instructions: various move instructions, trapa, div0s,
float, fdiv, ftrc.
Continuing on dev_rtc; removing the rtc demo.
20061008 Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
programs using KOS libs need this.)
Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
fmul, fadd, various floating-point moves, etc. A 256-byte
demo for Dreamcast runs :-)
20061012 Adding the SH "lds Rm,pr" and bsr instructions.
20061013 More SH instructions: "sts fpscr,rn", tas.b, and some more
floating point instructions, cmp/str, and more moves.
Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014 Generalizing the expression evaluator (used in the built-in
debugger) to support parentheses and +-*/%^&|.
20061015 Removing the experimental tlb index hint code in
mips_memory_v2p.c, since it didn't really have any effect.
20061017 Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
frchg, and some other instructions. Fixing missing sign-
extension in an 8-bit load instruction.
20061019 Adding a simple dev_dreamcast_rtc.
Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021 Continuing on various SH and Dreamcast things: sh4 timers,
debug messages for dev_pvr, fixing some virtual address
translation bugs, adding the bsrf instruction.
The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
Adding a dummy dev_dreamcast_asic.c (not really useful yet).
Implementing simple support for Store Queues.
Beginning on the PVR Tile Accelerator.
20061022 Generalizing the PVR framebuffer to support off-screen drawing,
multiple bit-depths, etc. (A small speed penalty, but most
likely worth it.)
Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
fschg, and some more); correcting bugs in "fsca" and "float".
20061024 Adding the SH ftrv (matrix * vector) instruction. Marcus
Comstedt's "tatest" example runs :) (wireframe only).
Correcting disassembly for SH floating point instructions that
use the xd* registers.
Adding the SH fsts instruction.
In memory_device_dyntrans_access(), only the currently used
range is now invalidated, and not the entire device range.
20061025 Adding a dummy AVR32 cpu mode skeleton.
20061026 Various Dreamcast updates; beginning on a Maple bus controller.
20061027 Continuing on the Maple bus. A bogus Controller, Keyboard, and
Mouse can now be detected by NetBSD and KOS homebrew programs.
Cleaning up the SH4 Timer Management Unit, and beginning on
SH4 interrupts.
Implementing the Dreamcast SYSASIC.
20061028 Continuing on the SYSASIC.
Adding the SH fsqrt instruction.
memory_sh.c now actually scans the ITLB.
Fixing a bug in dev_sh4.c, related to associative writes into
the memory-mapped UTLB array. NetBSD/dreamcast now reaches
userland stably, and prints the "Terminal type?" message :-]
Implementing enough of the Dreamcast keyboard to make NetBSD
accept it for input.
Enabling SuperH for stable (non-development) builds.
Adding NetBSD/dreamcast to the documentation, although it
doesn't support root-on-nfs yet.
20061029 Changing usleep(1) calls in the debugger to to usleep(10000)
(according to Brian Foley, this makes GXemul run better on
MacOS X).
Making the Maple "Controller" do something (enough to barely
interact with dcircus.elf).
20061030-31 Some progress on the PVR. More test programs start running (but
with strange output).
Various other SH4-related updates.
20061102 Various Dreamcast and SH4 updates; more KOS demos run now.
20061104 Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105 Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
Testing for the release.
============== RELEASE 0.4.3 ==============
| 1 | dpavlin | 14 | #ifndef CPU_SH_H |
| 2 | #define CPU_SH_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | dpavlin | 22 | * Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
| 6 | dpavlin | 14 | * |
| 7 | * Redistribution and use in source and binary forms, with or without | ||
| 8 | * modification, are permitted provided that the following conditions are met: | ||
| 9 | * | ||
| 10 | * 1. Redistributions of source code must retain the above copyright | ||
| 11 | * notice, this list of conditions and the following disclaimer. | ||
| 12 | * 2. Redistributions in binary form must reproduce the above copyright | ||
| 13 | * notice, this list of conditions and the following disclaimer in the | ||
| 14 | * documentation and/or other materials provided with the distribution. | ||
| 15 | * 3. The name of the author may not be used to endorse or promote products | ||
| 16 | * derived from this software without specific prior written permission. | ||
| 17 | * | ||
| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND | ||
| 19 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | ||
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE | ||
| 22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | ||
| 23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | ||
| 24 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | ||
| 25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | ||
| 26 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | ||
| 27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | ||
| 28 | * SUCH DAMAGE. | ||
| 29 | * | ||
| 30 | * | ||
| 31 | dpavlin | 32 | * $Id: cpu_sh.h,v 1.33 2006/10/27 15:51:37 debug Exp $ |
| 32 | * | ||
| 33 | * Note: Many things here are SH4-specific, so it probably doesn't work | ||
| 34 | * for SH3 emulation. | ||
| 35 | dpavlin | 14 | */ |
| 36 | |||
| 37 | #include "misc.h" | ||
| 38 | dpavlin | 32 | #include "sh4_cpu.h" |
| 39 | dpavlin | 14 | |
| 40 | |||
| 41 | struct cpu_family; | ||
| 42 | |||
| 43 | dpavlin | 30 | /* SH CPU types: */ |
| 44 | struct sh_cpu_type_def { | ||
| 45 | char *name; | ||
| 46 | int bits; | ||
| 47 | dpavlin | 32 | int arch; |
| 48 | uint32_t pvr; | ||
| 49 | uint32_t prr; | ||
| 50 | dpavlin | 30 | }; |
| 51 | dpavlin | 14 | |
| 52 | dpavlin | 32 | #define SH_CPU_TYPE_DEFS { \ |
| 53 | { "SH7750", 32, 4, SH4_PVR_SH7750, 0 }, \ | ||
| 54 | { "SH5", 64, 5, 0, 0 }, \ | ||
| 55 | { NULL, 0, 0, 0, 0 } } | ||
| 56 | dpavlin | 30 | |
| 57 | |||
| 58 | /* | ||
| 59 | * TODO: Figure out how to nicely support multiple instruction encodings! | ||
| 60 | * For now, I'm reverting this to SH4. SH5 will have to wait until later. | ||
| 61 | */ | ||
| 62 | |||
| 63 | #define SH_N_IC_ARGS 2 /* 3 for SH5/SH64 */ | ||
| 64 | #define SH_INSTR_ALIGNMENT_SHIFT 1 /* 2 for SH5/SH64 */ | ||
| 65 | #define SH_IC_ENTRIES_SHIFT 11 /* 10 for SH5/SH64 */ | ||
| 66 | dpavlin | 14 | #define SH_IC_ENTRIES_PER_PAGE (1 << SH_IC_ENTRIES_SHIFT) |
| 67 | #define SH_PC_TO_IC_ENTRY(a) (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \ | ||
| 68 | & (SH_IC_ENTRIES_PER_PAGE-1)) | ||
| 69 | #define SH_ADDR_TO_PAGENR(a) ((a) >> (SH_IC_ENTRIES_SHIFT \ | ||
| 70 | + SH_INSTR_ALIGNMENT_SHIFT)) | ||
| 71 | |||
| 72 | dpavlin | 32 | DYNTRANS_MISC_DECLARATIONS(sh,SH,uint32_t) |
| 73 | dpavlin | 24 | |
| 74 | dpavlin | 22 | #define SH_MAX_VPH_TLB_ENTRIES 128 |
| 75 | dpavlin | 14 | |
| 76 | |||
| 77 | dpavlin | 32 | #define SH_N_GPRS 16 |
| 78 | #define SH_N_GPRS_BANKED 8 | ||
| 79 | #define SH_N_FPRS 16 | ||
| 80 | dpavlin | 30 | |
| 81 | dpavlin | 32 | #define SH_N_ITLB_ENTRIES 4 |
| 82 | #define SH_N_UTLB_ENTRIES 64 | ||
| 83 | dpavlin | 30 | |
| 84 | dpavlin | 32 | |
| 85 | dpavlin | 14 | struct sh_cpu { |
| 86 | dpavlin | 30 | struct sh_cpu_type_def cpu_type; |
| 87 | |||
| 88 | /* compact = 1 if currently executing 16-bit long opcodes */ | ||
| 89 | dpavlin | 14 | int compact; |
| 90 | |||
| 91 | dpavlin | 32 | /* General Purpose Registers: */ |
| 92 | uint32_t r[SH_N_GPRS]; | ||
| 93 | uint32_t r_bank[SH_N_GPRS_BANKED]; | ||
| 94 | dpavlin | 14 | |
| 95 | dpavlin | 32 | /* Floating-Point Registers: */ |
| 96 | uint32_t fr[SH_N_FPRS]; | ||
| 97 | uint32_t xf[SH_N_FPRS]; /* "Other bank." */ | ||
| 98 | dpavlin | 14 | |
| 99 | dpavlin | 30 | uint32_t mach; /* Multiply-Accumulate High */ |
| 100 | uint32_t macl; /* Multiply-Accumulate Low */ | ||
| 101 | uint32_t pr; /* Procedure Register */ | ||
| 102 | uint32_t fpscr; /* Floating-point Status/Control */ | ||
| 103 | uint32_t fpul; /* Floating-point Communication Reg */ | ||
| 104 | uint32_t sr; /* Status Register */ | ||
| 105 | uint32_t ssr; /* Saved Status Register */ | ||
| 106 | uint32_t spc; /* Saved PC */ | ||
| 107 | uint32_t gbr; /* Global Base Register */ | ||
| 108 | uint32_t vbr; /* Vector Base Register */ | ||
| 109 | uint32_t sgr; /* Saved General Register */ | ||
| 110 | uint32_t dbr; /* Debug Base Register */ | ||
| 111 | |||
| 112 | dpavlin | 32 | /* Cache control: */ |
| 113 | uint32_t ccr; /* Cache Control Register */ | ||
| 114 | uint32_t qacr0; /* Queue Address Control Register 0 */ | ||
| 115 | uint32_t qacr1; /* Queue Address Control Register 1 */ | ||
| 116 | dpavlin | 30 | |
| 117 | dpavlin | 32 | /* MMU/TLB registers: */ |
| 118 | uint32_t pteh; /* Page Table Entry High */ | ||
| 119 | uint32_t ptel; /* Page Table Entry Low */ | ||
| 120 | uint32_t ptea; /* Page Table Entry A */ | ||
| 121 | uint32_t ttb; /* Translation Table Base */ | ||
| 122 | uint32_t tea; /* TLB Exception Address Register */ | ||
| 123 | uint32_t mmucr; /* MMU Control Register */ | ||
| 124 | uint32_t itlb_hi[SH_N_ITLB_ENTRIES]; | ||
| 125 | uint32_t itlb_lo[SH_N_ITLB_ENTRIES]; | ||
| 126 | uint32_t utlb_hi[SH_N_UTLB_ENTRIES]; | ||
| 127 | uint32_t utlb_lo[SH_N_UTLB_ENTRIES]; | ||
| 128 | |||
| 129 | /* Exception handling: */ | ||
| 130 | uint32_t tra; /* TRAPA Exception Register */ | ||
| 131 | uint32_t expevt; /* Exception Event Register */ | ||
| 132 | uint32_t intevt; /* Interrupt Event Register */ | ||
| 133 | |||
| 134 | /* Interrupt controller: */ | ||
| 135 | uint16_t intc_ipra; /* Interrupt Priority Registers */ | ||
| 136 | uint16_t intc_iprb; | ||
| 137 | uint16_t intc_iprc; | ||
| 138 | int16_t int_to_assert; /* Calculated int to assert */ | ||
| 139 | int int_level; /* Calculated int level */ | ||
| 140 | uint32_t int_pending[0x1000 / 0x20 / (sizeof(uint32_t)*8)]; | ||
| 141 | |||
| 142 | /* Timer/clock functionality: */ | ||
| 143 | int pclock; | ||
| 144 | |||
| 145 | |||
| 146 | dpavlin | 14 | /* |
| 147 | dpavlin | 22 | * Instruction translation cache and Virtual->Physical->Host |
| 148 | * address translation: | ||
| 149 | dpavlin | 14 | */ |
| 150 | dpavlin | 22 | DYNTRANS_ITC(sh) |
| 151 | VPH_TLBS(sh,SH) | ||
| 152 | VPH32(sh,SH,uint64_t,uint8_t) | ||
| 153 | dpavlin | 14 | }; |
| 154 | |||
| 155 | |||
| 156 | dpavlin | 30 | /* Status register bits: */ |
| 157 | #define SH_SR_T 0x00000001 /* True/false */ | ||
| 158 | #define SH_SR_S 0x00000002 /* Saturation */ | ||
| 159 | #define SH_SR_IMASK 0x000000f0 /* Interrupt mask */ | ||
| 160 | #define SH_SR_IMASK_SHIFT 4 | ||
| 161 | #define SH_SR_Q 0x00000100 /* State for Divide Step */ | ||
| 162 | #define SH_SR_M 0x00000200 /* State for Divide Step */ | ||
| 163 | #define SH_SR_FD 0x00008000 /* FPU Disable */ | ||
| 164 | #define SH_SR_BL 0x10000000 /* Exception/Interrupt Block */ | ||
| 165 | #define SH_SR_RB 0x20000000 /* Register Bank 0/1 */ | ||
| 166 | #define SH_SR_MD 0x40000000 /* Privileged Mode */ | ||
| 167 | |||
| 168 | dpavlin | 32 | /* Floating-point status/control register bits: */ |
| 169 | #define SH_FPSCR_RM_MASK 0x00000003 /* Rounding Mode */ | ||
| 170 | #define SH_FPSCR_RM_NEAREST 0x0 /* Round to nearest */ | ||
| 171 | #define SH_FPSCR_RM_ZERO 0x1 /* Round to zero */ | ||
| 172 | #define SH_FPSCR_INEXACT 0x00000004 /* Inexact exception */ | ||
| 173 | #define SH_FPSCR_UNDERFLOW 0x00000008 /* Underflow exception */ | ||
| 174 | #define SH_FPSCR_OVERFLOW 0x00000010 /* Overflow exception */ | ||
| 175 | #define SH_FPSCR_DIV_BY_ZERO 0x00000020 /* Div by zero exception */ | ||
| 176 | #define SH_FPSCR_INVALID 0x00000040 /* Invalid exception */ | ||
| 177 | #define SH_FPSCR_EN_INEXACT 0x00000080 /* Inexact enable */ | ||
| 178 | #define SH_FPSCR_EN_UNDERFLOW 0x00000100 /* Underflow enable */ | ||
| 179 | #define SH_FPSCR_EN_OVERFLOW 0x00000200 /* Overflow enable */ | ||
| 180 | #define SH_FPSCR_EN_DIV_BY_ZERO 0x00000400 /* Div by zero enable */ | ||
| 181 | #define SH_FPSCR_EN_INVALID 0x00000800 /* Invalid enable */ | ||
| 182 | #define SH_FPSCR_CAUSE_INEXACT 0x00001000 /* Cause Inexact */ | ||
| 183 | #define SH_FPSCR_CAUSE_UNDERFLOW 0x00002000 /* Cause Underflow */ | ||
| 184 | #define SH_FPSCR_CAUSE_OVERFLOW 0x00004000 /* Cause Overflow */ | ||
| 185 | #define SH_FPSCR_CAUSE_DIVBY0 0x00008000 /* Cause Div by 0 */ | ||
| 186 | #define SH_FPSCR_CAUSE_INVALID 0x00010000 /* Cause Invalid */ | ||
| 187 | #define SH_FPSCR_CAUSE_ERROR 0x00020000 /* Cause Error */ | ||
| 188 | #define SH_FPSCR_DN_ZERO 0x00040000 /* Denormalization Mode */ | ||
| 189 | #define SH_FPSCR_PR 0x00080000 /* Double-Precision Mode */ | ||
| 190 | #define SH_FPSCR_SZ 0x00100000 /* Double-Precision Size */ | ||
| 191 | #define SH_FPSCR_FR 0x00200000 /* Register Bank Select */ | ||
| 192 | dpavlin | 30 | |
| 193 | dpavlin | 32 | |
| 194 | dpavlin | 14 | /* cpu_sh.c: */ |
| 195 | dpavlin | 32 | int sh_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib); |
| 196 | dpavlin | 28 | int sh_run_instr(struct cpu *cpu); |
| 197 | dpavlin | 14 | void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
| 198 | unsigned char *host_page, int writeflag, uint64_t paddr_page); | ||
| 199 | dpavlin | 18 | void sh_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
| 200 | dpavlin | 14 | void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
| 201 | dpavlin | 28 | int sh32_run_instr(struct cpu *cpu); |
| 202 | dpavlin | 14 | void sh32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
| 203 | unsigned char *host_page, int writeflag, uint64_t paddr_page); | ||
| 204 | dpavlin | 18 | void sh32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
| 205 | dpavlin | 14 | void sh32_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
| 206 | dpavlin | 24 | void sh_init_64bit_dummy_tables(struct cpu *cpu); |
| 207 | dpavlin | 14 | int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
| 208 | unsigned char *data, size_t len, int writeflag, int cache_flags); | ||
| 209 | int sh_cpu_family_init(struct cpu_family *); | ||
| 210 | |||
| 211 | dpavlin | 30 | void sh_update_sr(struct cpu *cpu, uint32_t new_sr); |
| 212 | dpavlin | 32 | void sh_exception(struct cpu *cpu, int expevt, int intevt, uint32_t vaddr); |
| 213 | dpavlin | 14 | |
| 214 | dpavlin | 30 | /* memory_sh.c: */ |
| 215 | int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr, | ||
| 216 | uint64_t *return_addr, int flags); | ||
| 217 | |||
| 218 | |||
| 219 | dpavlin | 14 | #endif /* CPU_SH_H */ |
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