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dpavlin |
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#ifndef CPU_SH_H |
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#define CPU_SH_H |
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/* |
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dpavlin |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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dpavlin |
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* $Id: cpu_sh.h,v 1.21 2006/07/25 21:49:14 debug Exp $ |
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*/ |
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#include "misc.h" |
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struct cpu_family; |
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/* SH CPU types: */ |
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struct sh_cpu_type_def { |
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char *name; |
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int bits; |
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}; |
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dpavlin |
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dpavlin |
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#define SH_CPU_TYPE_DEFS { \ |
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{ "SH3", 32 }, \ |
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{ "SH4", 32 }, \ |
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{ "SH5", 64 }, \ |
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{ NULL, 0 } } |
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/* |
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* TODO: Figure out how to nicely support multiple instruction encodings! |
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* For now, I'm reverting this to SH4. SH5 will have to wait until later. |
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*/ |
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#define SH_N_IC_ARGS 2 /* 3 for SH5/SH64 */ |
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#define SH_INSTR_ALIGNMENT_SHIFT 1 /* 2 for SH5/SH64 */ |
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#define SH_IC_ENTRIES_SHIFT 11 /* 10 for SH5/SH64 */ |
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#define SH_IC_ENTRIES_PER_PAGE (1 << SH_IC_ENTRIES_SHIFT) |
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#define SH_PC_TO_IC_ENTRY(a) (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \ |
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& (SH_IC_ENTRIES_PER_PAGE-1)) |
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#define SH_ADDR_TO_PAGENR(a) ((a) >> (SH_IC_ENTRIES_SHIFT \ |
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+ SH_INSTR_ALIGNMENT_SHIFT)) |
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#define SH_L2N 17 |
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#define SH_L3N 18 |
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DYNTRANS_MISC_DECLARATIONS(sh,SH,uint64_t) |
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DYNTRANS_MISC64_DECLARATIONS(sh,SH,uint8_t) |
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#define SH_MAX_VPH_TLB_ENTRIES 128 |
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#define SH_N_GPRS 64 |
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struct sh_cpu { |
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struct sh_cpu_type_def cpu_type; |
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/* compact = 1 if currently executing 16-bit long opcodes */ |
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int compact; |
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uint32_t r_otherbank[8]; |
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uint64_t r[SH_N_GPRS]; |
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uint32_t mach; /* Multiply-Accumulate High */ |
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uint32_t macl; /* Multiply-Accumulate Low */ |
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uint32_t pr; /* Procedure Register */ |
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uint32_t fpscr; /* Floating-point Status/Control */ |
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uint32_t fpul; /* Floating-point Communication Reg */ |
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uint32_t sr; /* Status Register */ |
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uint32_t ssr; /* Saved Status Register */ |
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uint32_t spc; /* Saved PC */ |
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uint32_t gbr; /* Global Base Register */ |
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uint32_t vbr; /* Vector Base Register */ |
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uint32_t sgr; /* Saved General Register */ |
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uint32_t dbr; /* Debug Base Register */ |
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/* |
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* Instruction translation cache and Virtual->Physical->Host |
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* address translation: |
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*/ |
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DYNTRANS_ITC(sh) |
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VPH_TLBS(sh,SH) |
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VPH32(sh,SH,uint64_t,uint8_t) |
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VPH64(sh,SH,uint8_t) |
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}; |
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/* Status register bits: */ |
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#define SH_SR_T 0x00000001 /* True/false */ |
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#define SH_SR_S 0x00000002 /* Saturation */ |
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#define SH_SR_IMASK 0x000000f0 /* Interrupt mask */ |
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#define SH_SR_IMASK_SHIFT 4 |
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#define SH_SR_Q 0x00000100 /* State for Divide Step */ |
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#define SH_SR_M 0x00000200 /* State for Divide Step */ |
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#define SH_SR_FD 0x00008000 /* FPU Disable */ |
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#define SH_SR_BL 0x10000000 /* Exception/Interrupt Block */ |
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#define SH_SR_RB 0x20000000 /* Register Bank 0/1 */ |
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#define SH_SR_MD 0x40000000 /* Privileged Mode */ |
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/* cpu_sh.c: */ |
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int sh_run_instr(struct cpu *cpu); |
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void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void sh_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
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void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
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int sh32_run_instr(struct cpu *cpu); |
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void sh32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void sh32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
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void sh32_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
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void sh_init_64bit_dummy_tables(struct cpu *cpu); |
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int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, int writeflag, int cache_flags); |
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int sh_cpu_family_init(struct cpu_family *); |
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void sh_update_sr(struct cpu *cpu, uint32_t new_sr); |
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/* memory_sh.c: */ |
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int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr, |
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uint64_t *return_addr, int flags); |
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dpavlin |
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#endif /* CPU_SH_H */ |