/[gxemul]/trunk/src/include/cpu_ppc.h
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Contents of /trunk/src/include/cpu_ppc.h

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Revision 10 - (show annotations)
Mon Oct 8 16:18:27 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 5750 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.815 2005/06/27 23:04:35 debug Exp $
20050617	Experimenting some more with netbooting OpenBSD/sgi. Adding
		a hack which allows emulated ethernet networks to be
		distributed across multiple emulator processes.
20050618	Minor updates (documentation, dummy YAMON emulation, etc).
20050620	strcpy/strcat -> strlcpy/strlcat updates.
		Some more progress on evbmips (Malta).
20050621	Adding a section to doc/configfiles.html about ethernet
		emulation across multiple hosts.
		Beginning the work on the ARM translation engine (using the
		dynamic-but-not-binary translation method).
		Fixing a bintrans bug: 0x9fc00000 should always be treated as
		PROM area, just as 0xbfc00000 is.
		Minor progress on Malta emulation (the PCI-ISA bus).
20050622	NetBSD/evbmips can now be installed (using another emulated
		machine) and run (including userland and so on). :-)
		Spliting up the bintrans haddr_entry field into two (one for
		read, one for write). Probably not much of a speed increase,
		though.
		Updating some NetBSD 2.0 -> 2.0.2 in the documentation.
20050623	Minor updates (documentation, the TODO file, etc).
		gzipped kernels are now always automagically gunzipped when
		loaded.
20050624	Adding a dummy Playstation Portable (PSP) mode, just barely
		enough to run Hello World (in weird colors :-).
		Removing the -b command line option; old bintrans is enabled
		by default instead. It makes more sense.
		Trying to finally fix the non-working performance measurement
		thing (instr/second etc).
20050625	Continuing on the essential basics for ARM emulation. Two
		instructions seem to work, a branch and a simple "mov". (The
		mov arguments are not correct yet.) Performance is definitely
		reasonable.
		Various other minor updates.
		Adding the ARM "bl" instruction.
		Adding support for combining multiple ARM instructions into one
		function call. ("mov" + "mov" is the only one implemented so
		far, but it seems to work.)
		Cleaning up some IP32 interrupt things (crime/mace); disabling
		the PS/2 keyboard controller on IP32, so that NetBSD/sgimips
		boots into userland again.
20050626	Finally! NetBSD/sgimips netboots. Adding instructions to
		doc/guestoses.html on how to set up an nfs server etc.
		Various other minor fixes.
		Playstation Portable ".pbp" files can now be used directly.
		(The ELF part of the .pbp is extracted transparently.)
		Converting some sprintf -> snprintf.
		Adding some more instructions to the ARM disassembler.
20050627	More ARM updates. Adding some simple ldr(b), str(b),
		cmps, and conditional branch instructions, enough to run
		a simple Hello World program.
		All ARM instructions are now inlined/generated for all possible
		condition codes.
		Adding add and sub, and more load/store instructions.
		Removing dummy files: cpu_alpha.c, cpu_hppa.c, and cpu_sparc.c.
		Some minor documentation updates; preparing for a 0.3.4
		release. Updating some URLs.

==============  RELEASE 0.3.4  ==============


1 #ifndef CPU_PPC_H
2 #define CPU_PPC_H
3
4 /*
5 * Copyright (C) 2005 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cpu_ppc.h,v 1.23 2005/06/26 22:23:43 debug Exp $
32 */
33
34 #include "misc.h"
35
36
37 struct cpu_family;
38
39 #define MODE_PPC 0
40 #define MODE_POWER 1
41
42 /* PPC CPU types: */
43 struct ppc_cpu_type_def {
44 char *name;
45 int bits;
46 int flags;
47 int icache_shift;
48 int iway;
49 int dcache_shift;
50 int dway;
51 int l2cache_shift;
52 int l2way;
53 int altivec;
54
55 /* TODO: POWER vs PowerPC? */
56 };
57
58 /* Flags: */
59 #define PPC_NOFP 1
60 /* TODO: Most of these just bogus */
61
62 #define PPC_CPU_TYPE_DEFS { \
63 { "PPC405GP", 32, PPC_NOFP, 15, 2, 15, 2, 20, 1, 0 }, \
64 { "PPC603e", 32, 0, 14, 4, 14, 4, 0, 0, 0 }, \
65 { "MPC7400", 32, 0, 15, 2, 15, 2, 19, 1, 1 }, \
66 { "PPC750", 32, 0, 15, 2, 15, 2, 20, 1, 0 }, \
67 { "G4e", 32, 0, 15, 8, 15, 8, 18, 8, 1 }, \
68 { "PPC970", 64, 0, 16, 1, 15, 2, 19, 1, 1 }, \
69 { NULL, 0, 0, 0,0, 0,0, 0,0, 0 } \
70 };
71
72 #define PPC_NGPRS 32
73 #define PPC_NFPRS 32
74
75 struct ppc_cpu {
76 struct ppc_cpu_type_def cpu_type;
77
78 int trace_tree_depth;
79
80 uint64_t of_emul_addr;
81 uint64_t pc_last;
82
83 int mode; /* MODE_PPC or MODE_POWER */
84 int bits; /* 32 or 64 */
85
86 uint32_t cr; /* Condition Register */
87 uint32_t fpscr; /* FP Status and Control Register */
88 uint64_t lr; /* Link Register */
89 uint64_t ctr; /* Count Register */
90 uint64_t gpr[PPC_NGPRS]; /* General Purpose Registers */
91 uint64_t xer; /* FP Exception Register */
92 uint64_t fpr[PPC_NFPRS]; /* Floating-Point Registers */
93
94 uint32_t tbl; /* Time Base Lower */
95 uint32_t tbu; /* Time Base Upper */
96 uint32_t dec; /* Decrementer */
97 uint32_t hdec; /* Hypervisor Decrementer */
98 uint64_t ssr0; /* Machine status save/restore
99 register 0 */
100 uint64_t ssr1; /* Machine status save/restore
101 register 1 */
102 uint64_t msr; /* Machine state register */
103 uint64_t sprg0; /* Special Purpose Register G0 */
104 uint64_t sprg1; /* Special Purpose Register G1 */
105 uint64_t sprg2; /* Special Purpose Register G2 */
106 uint64_t sprg3; /* Special Purpose Register G3 */
107 uint32_t pvr; /* Processor Version Register */
108 uint32_t pir; /* Processor ID */
109 };
110
111
112 /* Machine status word bits: (according to Book 3) */
113 #define PPC_MSR_SF (1ULL << 63) /* Sixty-Four-Bit Mode */
114 /* bits 62..61 are reserved */
115 #define PPC_MSR_HV (1ULL << 60) /* Hypervisor */
116 /* bits 59..17 are reserved */
117 #define PPC_MSR_ILE (1 << 16) /* Interrupt Little-Endian Mode */
118 #define PPC_MSR_EE (1 << 15) /* External Interrupt Enable */
119 #define PPC_MSR_PR (1 << 14) /* Problem State */
120 #define PPC_MSR_FP (1 << 13) /* Floating-Point Available */
121 #define PPC_MSR_ME (1 << 12) /* Machine Check Interrupt Enable */
122 #define PPC_MSR_FE0 (1 << 11) /* Floating-Point Exception Mode 0 */
123 #define PPC_MSR_SE (1 << 10) /* Single-Step Trace Enable */
124 #define PPC_MSR_BE (1 << 9) /* Branch Trace Enable */
125 #define PPC_MSR_FE1 (1 << 8) /* Floating-Point Exception Mode 1 */
126 #define PPC_MSR_IR (1 << 5) /* Instruction Relocate */
127 #define PPC_MSR_DR (1 << 4) /* Data Relocate */
128 #define PPC_MSR_PMM (1 << 2) /* Performance Monitor Mark */
129 #define PPC_MSR_RI (1 << 1) /* Recoverable Interrupt */
130 #define PPC_MSR_LE (1) /* Little-Endian Mode */
131
132 /* XER bits: */
133 #define PPC_XER_SO (1 << 31) /* Summary Overflow */
134 #define PPC_XER_OV (1 << 30) /* Overflow */
135 #define PPC_XER_CA (1 << 29) /* Carry */
136
137
138 /* cpu_ppc.c: */
139 void ppc_cpu_show_full_statistics(struct machine *m);
140 void ppc_cpu_register_match(struct machine *m, char *name,
141 int writeflag, uint64_t *valuep, int *match_register);
142 void ppc_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs);
143 int ppc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
144 int running, uint64_t addr, int bintrans);
145 int ppc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr);
146 int ppc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr);
147 int ppc_cpu_run(struct emul *emul, struct machine *machine);
148 void ppc_cpu_dumpinfo(struct cpu *cpu);
149 void ppc_cpu_list_available_types(void);
150 int ppc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
151 unsigned char *data, size_t len, int writeflag, int cache_flags);
152 int ppc_cpu_family_init(struct cpu_family *);
153
154
155 #endif /* CPU_PPC_H */

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