/[gxemul]/trunk/src/include/cpu_ppc.h
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Contents of /trunk/src/include/cpu_ppc.h

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Revision 30 - (show annotations)
Mon Oct 8 16:20:40 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 8253 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1325 2006/08/15 15:38:37 debug Exp $
20060723	More Transputer instructions (pfix, nfix, opr, mint, ldl, ldlp,
		eqc, rev, ajw, stl, stlf, sthf, sub, ldnl, ldnlp, ldpi, move,
		wcnt, add, bcnt).
		Adding more SPARC instructions (andcc, addcc, bl, rdpr).
		Progress on the igsfb framebuffer used by NetBSD/netwinder.
		Enabling 8-bit fills in dev_fb.
		NetBSD/netwinder 3.0.1 can now run from a disk image :-)
20060724	Cleanup/performance fix for 64-bit virtual translation table
		updates (by removing the "timestamp" stuff). A full NetBSD/pmax
		3.0.1 install for R4400 has dropped from 667 seconds to 584 :)
		Fixing the igsfb "almost vga" color (it is 24-bit, not 18-bit).
		Adding some MIPS instruction combinations (3*lw, and 3*addu).
		The 8048 keyboard now turns off interrupt enable between the
		KBR_ACK and the KBR_RSTDONE, to work better with Linux 2.6.
		Not causing PPC DEC interrupts if PPC_NO_DEC is set for a
		specific CPU; NetBSD/bebox gets slightly further than before.
		Adding some more SPARC instructions: branches, udiv.
20060725	Refreshing dev_pckbc.c a little.
		Cleanups for the SH emulation mode, and adding the first
		"compact" (16-bit) instructions: various simple movs, nop,
		shll, stc, or, ldc.
20060726	Adding dummy "pcn" (AMD PCnet NIC) PCI glue.
20060727	Various cleanups; removing stuff from cpu.h, such as
		running_translated (not really meaningful anymore), and
		page flags (breaking into the debugger clears all translations
		anyway).
		Minor MIPS instruction combination updates.
20060807	Expanding the 3*sw and 3*lw MIPS instruction combinations to
		work with 2* and 4* too, resulting in a minor performance gain.
		Implementing a usleep hack for the RM52xx/MIPS32/MIPS64 "wait"
		instruction (when emulating 1 cpu).
20060808	Experimenting with some more MIPS instruction combinations.
		Implementing support for showing a (hardcoded 12x22) text
		cursor in igsfb.
20060809	Simplifying the NetBSD/evbmips (Malta) install instructions
		somewhat (by using a NetBSD/pmax ramdisk install kernel).
20060812	Experimenting more with the MIPS 'wait' instruction.
		PCI configuration register writes can now be handled, which
		allow PCI IDE controllers to work with NetBSD/Malta 3.0.1 and
		NetBSD/cobalt 3.0.1. (Previously only NetBSD 2.1 worked.)
20060813	Updating dev_gt.c based on numbers from Alec Voropay, to enable
		Linux 2.6 to use PCI on Malta.
		Continuing on Algor interrupt stuff.
20060814	Adding support for routing ISA interrupts to two different
		interrupts, making it possible to run NetBSD/algor :-)
20060814-15	Testing for the release.

==============  RELEASE 0.4.2  ==============


1 #ifndef CPU_PPC_H
2 #define CPU_PPC_H
3
4 /*
5 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cpu_ppc.h,v 1.67 2006/07/24 21:14:52 debug Exp $
32 */
33
34 #include "misc.h"
35
36
37 struct cpu_family;
38
39 #define MODE_PPC 0
40 #define MODE_POWER 1
41
42 /* PPC CPU types: */
43 struct ppc_cpu_type_def {
44 char *name;
45 int pvr;
46 int bits;
47 int flags;
48 int icache_shift;
49 int ilinesize;
50 int iway;
51 int dcache_shift;
52 int dlinesize;
53 int dway;
54 int l2cache_shift;
55 int l2linesize;
56 int l2way;
57 int altivec;
58
59 /* TODO: POWER vs PowerPC? */
60 };
61
62 /* Flags: */
63 #define PPC_NOFP 1
64 #define PPC_601 2
65 #define PPC_603 4
66 #define PPC_NO_DEC 8 /* No DEC (decrementer) SPR */
67
68 /*
69 * TODO: Most of these just bogus
70 *
71 * NOTE: PPC603e has the PPC_NO_DEC flag because that makes NetBSD/bebox
72 * work :) but I am not sure that it is correct.
73 */
74
75 #define PPC_CPU_TYPE_DEFS { \
76 { "PPC405GP", 0x40110000, 32, PPC_NOFP|PPC_NO_DEC, \
77 13,5,2, 13,5,2, 0,5,1, 0 }, \
78 { "PPC601", 0, 32, PPC_601, 14,5,4, 14,5,4, 0,0,0, 0 },\
79 { "PPC603", 0x00030302, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 },\
80 { "PPC603e", 0x00060104, 32, PPC_603|PPC_NO_DEC, \
81 14,5,4, 14,5,4, 0,0,0, 0 }, \
82 { "PPC604", 0x00040304, 32, 0, 15,5,4, 15,5,4, 0,0,0, 0 }, \
83 { "PPC620", 0x00140000, 64, 0, 15,5,4, 15,5,4, 0,0,0, 0 }, \
84 { "MPC7400", 0x000c0000, 32, 0, 15,5,2, 15,5,2, 19,5,1, 1 }, \
85 { "PPC750", 0x00084202, 32, 0, 15,5,2, 15,5,2, 20,5,1, 0 }, \
86 { "G4e", 0, 32, 0, 15,5,8, 15,5,8, 18,5,8, 1 }, \
87 { "PPC970", 0x00390000, 64, 0, 16,7,1, 15,7,2, 19,7,1, 1 }, \
88 { NULL, 0, 0,0,0,0,0,0,0,0,0,0,0,0 } \
89 }
90
91 #define PPC_NGPRS 32
92 #define PPC_NFPRS 32
93 #define PPC_NVRS 32
94 #define PPC_N_TGPRS 4
95
96 #define PPC_N_IC_ARGS 3
97 #define PPC_INSTR_ALIGNMENT_SHIFT 2
98 #define PPC_IC_ENTRIES_SHIFT 10
99 #define PPC_IC_ENTRIES_PER_PAGE (1 << PPC_IC_ENTRIES_SHIFT)
100 #define PPC_PC_TO_IC_ENTRY(a) (((a)>>PPC_INSTR_ALIGNMENT_SHIFT) \
101 & (PPC_IC_ENTRIES_PER_PAGE-1))
102 #define PPC_ADDR_TO_PAGENR(a) ((a) >> (PPC_IC_ENTRIES_SHIFT \
103 + PPC_INSTR_ALIGNMENT_SHIFT))
104
105 #define PPC_L2N 17
106 #define PPC_L3N 18
107
108 DYNTRANS_MISC_DECLARATIONS(ppc,PPC,uint64_t)
109 DYNTRANS_MISC64_DECLARATIONS(ppc,PPC,uint8_t)
110
111 #define PPC_MAX_VPH_TLB_ENTRIES 128
112
113
114 struct ppc_cpu {
115 struct ppc_cpu_type_def cpu_type;
116
117 uint64_t of_emul_addr;
118
119 int mode; /* MODE_PPC or MODE_POWER */
120 int bits; /* 32 or 64 */
121
122 int irq_asserted; /* External Interrupt flag */
123 int dec_intr_pending;/* Decrementer interrupt pending */
124 uint64_t zero; /* A zero register */
125
126 uint32_t cr; /* Condition Register */
127 uint32_t fpscr; /* FP Status and Control Register */
128 uint64_t gpr[PPC_NGPRS]; /* General Purpose Registers */
129 uint64_t fpr[PPC_NFPRS]; /* Floating-Point Registers */
130
131 uint64_t vr_hi[PPC_NVRS];/* 128-bit Vector registers */
132 uint64_t vr_lo[PPC_NVRS];/* (Hi and lo 64-bit parts) */
133
134 uint64_t msr; /* Machine state register */
135 uint64_t tgpr[PPC_N_TGPRS];/*Temporary gpr 0..3 */
136
137 uint32_t sr[16]; /* Segment registers. */
138 uint64_t spr[1024];
139
140 uint64_t ll_addr; /* Load-linked / store-conditional */
141 int ll_bit;
142
143
144 /*
145 * Instruction translation cache and Virtual->Physical->Host
146 * address translation:
147 */
148 DYNTRANS_ITC(ppc)
149 VPH_TLBS(ppc,PPC)
150 VPH32(ppc,PPC,uint64_t,uint8_t)
151 VPH64(ppc,PPC,uint8_t)
152 };
153
154
155 /* Machine status word bits: (according to Book 3) */
156 #define PPC_MSR_SF (1ULL << 63) /* Sixty-Four-Bit Mode */
157 /* bits 62..61 are reserved */
158 #define PPC_MSR_HV (1ULL << 60) /* Hypervisor */
159 /* bits 59..17 are reserved */
160 #define PPC_MSR_VEC (1 << 25) /* Altivec Enable */
161 #define PPC_MSR_TGPR (1 << 17) /* Temporary gpr0..3 */
162 #define PPC_MSR_ILE (1 << 16) /* Interrupt Little-Endian Mode */
163 #define PPC_MSR_EE (1 << 15) /* External Interrupt Enable */
164 #define PPC_MSR_PR (1 << 14) /* Problem/Privilege State */
165 #define PPC_MSR_FP (1 << 13) /* Floating-Point Available */
166 #define PPC_MSR_ME (1 << 12) /* Machine Check Interrupt Enable */
167 #define PPC_MSR_FE0 (1 << 11) /* Floating-Point Exception Mode 0 */
168 #define PPC_MSR_SE (1 << 10) /* Single-Step Trace Enable */
169 #define PPC_MSR_BE (1 << 9) /* Branch Trace Enable */
170 #define PPC_MSR_FE1 (1 << 8) /* Floating-Point Exception Mode 1 */
171 #define PPC_MSR_IP (1 << 6) /* Vector Table at 0xfff00000 */
172 #define PPC_MSR_IR (1 << 5) /* Instruction Relocate */
173 #define PPC_MSR_DR (1 << 4) /* Data Relocate */
174 #define PPC_MSR_PMM (1 << 2) /* Performance Monitor Mark */
175 #define PPC_MSR_RI (1 << 1) /* Recoverable Interrupt */
176 #define PPC_MSR_LE (1) /* Little-Endian Mode */
177
178 /* Floating-point Status: */
179 #define PPC_FPSCR_FX (1 << 31) /* Exception summary */
180 #define PPC_FPSCR_FEX (1 << 30) /* Enabled Exception summary */
181 #define PPC_FPSCR_VX (1 << 29) /* Invalid Operation summary */
182 /* .. TODO */
183 #define PPC_FPSCR_VXNAN (1 << 24)
184 /* .. TODO */
185 #define PPC_FPSCR_FPCC 0x0000f000
186 #define PPC_FPSCR_FPCC_SHIFT 12
187 #define PPC_FPSCR_FL (1 << 15) /* Less than */
188 #define PPC_FPSCR_FG (1 << 14) /* Greater than */
189 #define PPC_FPSCR_FE (1 << 13) /* Equal or Zero */
190 #define PPC_FPSCR_FU (1 << 12) /* Unordered or NaN */
191
192 /* Exceptions: */
193 #define PPC_EXCEPTION_DSI 0x3 /* Data Storage Interrupt */
194 #define PPC_EXCEPTION_ISI 0x4 /* Instruction Storage Interrupt */
195 #define PPC_EXCEPTION_EI 0x5 /* External interrupt */
196 #define PPC_EXCEPTION_FPU 0x8 /* Floating-Point unavailable */
197 #define PPC_EXCEPTION_DEC 0x9 /* Decrementer */
198 #define PPC_EXCEPTION_SC 0xc /* Syscall */
199
200 /* XER bits: */
201 #define PPC_XER_SO (1UL << 31) /* Summary Overflow */
202 #define PPC_XER_OV (1 << 30) /* Overflow */
203 #define PPC_XER_CA (1 << 29) /* Carry */
204
205
206 /* cpu_ppc.c: */
207 int ppc_run_instr(struct cpu *cpu);
208 int ppc32_run_instr(struct cpu *cpu);
209 void ppc_exception(struct cpu *cpu, int exception_nr);
210 void ppc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
211 unsigned char *host_page, int writeflag, uint64_t paddr_page);
212 void ppc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
213 unsigned char *host_page, int writeflag, uint64_t paddr_page);
214 void ppc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
215 void ppc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
216 void ppc_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
217 void ppc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
218 void ppc_init_64bit_dummy_tables(struct cpu *cpu);
219 int ppc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
220 unsigned char *data, size_t len, int writeflag, int cache_flags);
221 int ppc_cpu_family_init(struct cpu_family *);
222
223 /* memory_ppc.c: */
224 int ppc_translate_v2p(struct cpu *cpu, uint64_t vaddr,
225 uint64_t *return_addr, int flags);
226
227 #endif /* CPU_PPC_H */

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