src/include/cpu_ppc.h

#ifndef CPU_PPC_H
#define CPU_PPC_H

/*
 *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_ppc.h,v 1.66 2006/07/16 13:32:28 debug Exp $
 */

#include "misc.h"


struct cpu_family;

#define MODE_PPC                0
#define MODE_POWER              1

/*  PPC CPU types:  */
struct ppc_cpu_type_def { 
        char            *name;
        int             pvr;
        int             bits;
        int             flags;
        int             icache_shift;
        int             ilinesize;
        int             iway;
        int             dcache_shift;
        int             dlinesize;
        int             dway;
        int             l2cache_shift;
        int             l2linesize;
        int             l2way;
        int             altivec;

        /*  TODO: POWER vs PowerPC?  */
};

/*  Flags:  */
#define PPC_NOFP                1
#define PPC_601                 2
#define PPC_603                 4
#define PPC_NO_DEC              8       /*  No DEC (decrementer) SPR  */

/*  TODO: Most of these just bogus  */

#define PPC_CPU_TYPE_DEFS       {                                       \
        { "PPC405GP",   0x40110000, 32, PPC_NOFP|PPC_NO_DEC,            \
                                        13,5,2, 13,5,2, 0,5,1, 0 },     \
        { "PPC601",     0,          32, PPC_601, 14,5,4, 14,5,4, 0,0,0, 0 },\
        { "PPC603",     0x00030302, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 },\
        { "PPC603e",    0x00060104, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 },\
        { "PPC604",     0x00040304, 32, 0, 15,5,4, 15,5,4, 0,0,0, 0 },  \
        { "PPC620",     0x00140000, 64, 0, 15,5,4, 15,5,4, 0,0,0, 0 },  \
        { "MPC7400",    0x000c0000, 32, 0, 15,5,2, 15,5,2, 19,5,1, 1 }, \
        { "PPC750",     0x00084202, 32, 0, 15,5,2, 15,5,2, 20,5,1, 0 }, \
        { "G4e",        0,          32, 0, 15,5,8, 15,5,8, 18,5,8, 1 }, \
        { "PPC970",     0x00390000, 64, 0, 16,7,1, 15,7,2, 19,7,1, 1 }, \
        { NULL,         0,          0,0,0,0,0,0,0,0,0,0,0,0 }           \
        }

#define PPC_NGPRS               32
#define PPC_NFPRS               32
#define PPC_NVRS                32
#define PPC_N_TGPRS             4

#define PPC_N_IC_ARGS                   3
#define PPC_INSTR_ALIGNMENT_SHIFT       2
#define PPC_IC_ENTRIES_SHIFT            10
#define PPC_IC_ENTRIES_PER_PAGE         (1 << PPC_IC_ENTRIES_SHIFT)
#define PPC_PC_TO_IC_ENTRY(a)           (((a)>>PPC_INSTR_ALIGNMENT_SHIFT) \
                                        & (PPC_IC_ENTRIES_PER_PAGE-1))
#define PPC_ADDR_TO_PAGENR(a)           ((a) >> (PPC_IC_ENTRIES_SHIFT \
                                        + PPC_INSTR_ALIGNMENT_SHIFT))

#define PPC_L2N                 17
#define PPC_L3N                 18

DYNTRANS_MISC_DECLARATIONS(ppc,PPC,uint64_t)
DYNTRANS_MISC64_DECLARATIONS(ppc,PPC,uint8_t)

#define PPC_MAX_VPH_TLB_ENTRIES         128


struct ppc_cpu {
        struct ppc_cpu_type_def cpu_type;

        uint64_t        of_emul_addr;

        int             mode;           /*  MODE_PPC or MODE_POWER  */
        int             bits;           /*  32 or 64  */

        int             irq_asserted;   /*  External Interrupt flag  */
        int             dec_intr_pending;/* Decrementer interrupt pending  */
        uint64_t        zero;           /*  A zero register  */

        uint32_t        cr;             /*  Condition Register  */
        uint32_t        fpscr;          /*  FP Status and Control Register  */
        uint64_t        gpr[PPC_NGPRS]; /*  General Purpose Registers  */
        uint64_t        fpr[PPC_NFPRS]; /*  Floating-Point Registers  */

        uint64_t        vr_hi[PPC_NVRS];/*  128-bit Vector registers  */
        uint64_t        vr_lo[PPC_NVRS];/*  (Hi and lo 64-bit parts)  */

        uint64_t        msr;            /*  Machine state register  */
        uint64_t        tgpr[PPC_N_TGPRS];/*Temporary gpr 0..3  */

        uint32_t        sr[16];         /*  Segment registers.  */
        uint64_t        spr[1024];

        uint64_t        ll_addr;        /*  Load-linked / store-conditional  */
        int             ll_bit;


        /*
         *  Instruction translation cache and Virtual->Physical->Host
         *  address translation:
         */
        DYNTRANS_ITC(ppc)
        VPH_TLBS(ppc,PPC)
        VPH32(ppc,PPC,uint64_t,uint8_t)
        VPH64(ppc,PPC,uint8_t)
};


/*  Machine status word bits: (according to Book 3)  */
#define PPC_MSR_SF      (1ULL << 63)    /*  Sixty-Four-Bit Mode  */
/*  bits 62..61 are reserved  */
#define PPC_MSR_HV      (1ULL << 60)    /*  Hypervisor  */
/*  bits 59..17  are reserved  */
#define PPC_MSR_VEC     (1 << 25)       /*  Altivec Enable  */
#define PPC_MSR_TGPR    (1 << 17)       /*  Temporary gpr0..3  */
#define PPC_MSR_ILE     (1 << 16)       /*  Interrupt Little-Endian Mode  */
#define PPC_MSR_EE      (1 << 15)       /*  External Interrupt Enable  */
#define PPC_MSR_PR      (1 << 14)       /*  Problem/Privilege State  */
#define PPC_MSR_FP      (1 << 13)       /*  Floating-Point Available  */
#define PPC_MSR_ME      (1 << 12)       /*  Machine Check Interrupt Enable  */
#define PPC_MSR_FE0     (1 << 11)       /*  Floating-Point Exception Mode 0  */
#define PPC_MSR_SE      (1 << 10)       /*  Single-Step Trace Enable  */
#define PPC_MSR_BE      (1 << 9)        /*  Branch Trace Enable  */
#define PPC_MSR_FE1     (1 << 8)        /*  Floating-Point Exception Mode 1  */
#define PPC_MSR_IP      (1 << 6)        /*  Vector Table at 0xfff00000  */
#define PPC_MSR_IR      (1 << 5)        /*  Instruction Relocate  */
#define PPC_MSR_DR      (1 << 4)        /*  Data Relocate  */
#define PPC_MSR_PMM     (1 << 2)        /*  Performance Monitor Mark  */
#define PPC_MSR_RI      (1 << 1)        /*  Recoverable Interrupt  */
#define PPC_MSR_LE      (1)             /*  Little-Endian Mode  */

/*  Floating-point Status:  */
#define PPC_FPSCR_FX    (1 << 31)       /*  Exception summary  */
#define PPC_FPSCR_FEX   (1 << 30)       /*  Enabled Exception summary  */
#define PPC_FPSCR_VX    (1 << 29)       /*  Invalid Operation summary  */
/*  .. TODO  */
#define PPC_FPSCR_VXNAN (1 << 24)
/*  .. TODO  */
#define PPC_FPSCR_FPCC  0x0000f000
#define PPC_FPSCR_FPCC_SHIFT    12
#define PPC_FPSCR_FL    (1 << 15)       /*  Less than  */
#define PPC_FPSCR_FG    (1 << 14)       /*  Greater than  */
#define PPC_FPSCR_FE    (1 << 13)       /*  Equal or Zero  */
#define PPC_FPSCR_FU    (1 << 12)       /*  Unordered or NaN  */

/*  Exceptions:  */
#define PPC_EXCEPTION_DSI       0x3     /*  Data Storage Interrupt  */
#define PPC_EXCEPTION_ISI       0x4     /*  Instruction Storage Interrupt  */
#define PPC_EXCEPTION_EI        0x5     /*  External interrupt  */
#define PPC_EXCEPTION_FPU       0x8     /*  Floating-Point unavailable  */
#define PPC_EXCEPTION_DEC       0x9     /*  Decrementer  */
#define PPC_EXCEPTION_SC        0xc     /*  Syscall  */

/*  XER bits:  */
#define PPC_XER_SO      (1UL << 31)     /*  Summary Overflow  */
#define PPC_XER_OV      (1 << 30)       /*  Overflow  */
#define PPC_XER_CA      (1 << 29)       /*  Carry  */


/*  cpu_ppc.c:  */
int ppc_run_instr(struct cpu *cpu);
int ppc32_run_instr(struct cpu *cpu);
void ppc_exception(struct cpu *cpu, int exception_nr);
void ppc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void ppc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void ppc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
void ppc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
void ppc_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
void ppc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
void ppc_init_64bit_dummy_tables(struct cpu *cpu);
int ppc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
        unsigned char *data, size_t len, int writeflag, int cache_flags);
int ppc_cpu_family_init(struct cpu_family *);

/*  memory_ppc.c:  */
int ppc_translate_v2p(struct cpu *cpu, uint64_t vaddr,
        uint64_t *return_addr, int flags);

#endif  /*  CPU_PPC_H  */
1	#ifndef CPU_PPC_H
2	#define CPU_PPC_H
3
4	/*
5	* Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
6	*
7	* Redistribution and use in source and binary forms, with or without
8	* modification, are permitted provided that the following conditions are met:
9	*
10	* 1. Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	* 3. The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28	* SUCH DAMAGE.
29	*
30	*
31	* $Id: cpu_ppc.h,v 1.66 2006/07/16 13:32:28 debug Exp $
32	*/
33
34	#include "misc.h"
35
36
37	struct cpu_family;
38
39	#define MODE_PPC 0
40	#define MODE_POWER 1
41
42	/* PPC CPU types: */
43	struct ppc_cpu_type_def {
44	char *name;
45	int pvr;
46	int bits;
47	int flags;
48	int icache_shift;
49	int ilinesize;
50	int iway;
51	int dcache_shift;
52	int dlinesize;
53	int dway;
54	int l2cache_shift;
55	int l2linesize;
56	int l2way;
57	int altivec;
58
59	/* TODO: POWER vs PowerPC? */
60	};
61
62	/* Flags: */
63	#define PPC_NOFP 1
64	#define PPC_601 2
65	#define PPC_603 4
66	#define PPC_NO_DEC 8 /* No DEC (decrementer) SPR */
67
68	/* TODO: Most of these just bogus */
69
70	#define PPC_CPU_TYPE_DEFS { \
71	{ "PPC405GP", 0x40110000, 32, PPC_NOFP\|PPC_NO_DEC, \
72	13,5,2, 13,5,2, 0,5,1, 0 }, \
73	{ "PPC601", 0, 32, PPC_601, 14,5,4, 14,5,4, 0,0,0, 0 },\
74	{ "PPC603", 0x00030302, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 },\
75	{ "PPC603e", 0x00060104, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 },\
76	{ "PPC604", 0x00040304, 32, 0, 15,5,4, 15,5,4, 0,0,0, 0 }, \
77	{ "PPC620", 0x00140000, 64, 0, 15,5,4, 15,5,4, 0,0,0, 0 }, \
78	{ "MPC7400", 0x000c0000, 32, 0, 15,5,2, 15,5,2, 19,5,1, 1 }, \
79	{ "PPC750", 0x00084202, 32, 0, 15,5,2, 15,5,2, 20,5,1, 0 }, \
80	{ "G4e", 0, 32, 0, 15,5,8, 15,5,8, 18,5,8, 1 }, \
81	{ "PPC970", 0x00390000, 64, 0, 16,7,1, 15,7,2, 19,7,1, 1 }, \
82	{ NULL, 0, 0,0,0,0,0,0,0,0,0,0,0,0 } \
83	}
84
85	#define PPC_NGPRS 32
86	#define PPC_NFPRS 32
87	#define PPC_NVRS 32
88	#define PPC_N_TGPRS 4
89
90	#define PPC_N_IC_ARGS 3
91	#define PPC_INSTR_ALIGNMENT_SHIFT 2
92	#define PPC_IC_ENTRIES_SHIFT 10
93	#define PPC_IC_ENTRIES_PER_PAGE (1 << PPC_IC_ENTRIES_SHIFT)
94	#define PPC_PC_TO_IC_ENTRY(a) (((a)>>PPC_INSTR_ALIGNMENT_SHIFT) \
95	& (PPC_IC_ENTRIES_PER_PAGE-1))
96	#define PPC_ADDR_TO_PAGENR(a) ((a) >> (PPC_IC_ENTRIES_SHIFT \
97	+ PPC_INSTR_ALIGNMENT_SHIFT))
98
99	#define PPC_L2N 17
100	#define PPC_L3N 18
101
102	DYNTRANS_MISC_DECLARATIONS(ppc,PPC,uint64_t)
103	DYNTRANS_MISC64_DECLARATIONS(ppc,PPC,uint8_t)
104
105	#define PPC_MAX_VPH_TLB_ENTRIES 128
106
107
108	struct ppc_cpu {
109	struct ppc_cpu_type_def cpu_type;
110
111	uint64_t of_emul_addr;
112
113	int mode; /* MODE_PPC or MODE_POWER */
114	int bits; /* 32 or 64 */
115
116	int irq_asserted; /* External Interrupt flag */
117	int dec_intr_pending;/* Decrementer interrupt pending */
118	uint64_t zero; /* A zero register */
119
120	uint32_t cr; /* Condition Register */
121	uint32_t fpscr; /* FP Status and Control Register */
122	uint64_t gpr[PPC_NGPRS]; /* General Purpose Registers */
123	uint64_t fpr[PPC_NFPRS]; /* Floating-Point Registers */
124
125	uint64_t vr_hi[PPC_NVRS];/* 128-bit Vector registers */
126	uint64_t vr_lo[PPC_NVRS];/* (Hi and lo 64-bit parts) */
127
128	uint64_t msr; /* Machine state register */
129	uint64_t tgpr[PPC_N_TGPRS];/Temporary gpr 0..3 /
130
131	uint32_t sr[16]; /* Segment registers. */
132	uint64_t spr[1024];
133
134	uint64_t ll_addr; /* Load-linked / store-conditional */
135	int ll_bit;
136
137
138	/*
139	* Instruction translation cache and Virtual->Physical->Host
140	* address translation:
141	*/
142	DYNTRANS_ITC(ppc)
143	VPH_TLBS(ppc,PPC)
144	VPH32(ppc,PPC,uint64_t,uint8_t)
145	VPH64(ppc,PPC,uint8_t)
146	};
147
148
149	/* Machine status word bits: (according to Book 3) */
150	#define PPC_MSR_SF (1ULL << 63) /* Sixty-Four-Bit Mode */
151	/* bits 62..61 are reserved */
152	#define PPC_MSR_HV (1ULL << 60) /* Hypervisor */
153	/* bits 59..17 are reserved */
154	#define PPC_MSR_VEC (1 << 25) /* Altivec Enable */
155	#define PPC_MSR_TGPR (1 << 17) /* Temporary gpr0..3 */
156	#define PPC_MSR_ILE (1 << 16) /* Interrupt Little-Endian Mode */
157	#define PPC_MSR_EE (1 << 15) /* External Interrupt Enable */
158	#define PPC_MSR_PR (1 << 14) /* Problem/Privilege State */
159	#define PPC_MSR_FP (1 << 13) /* Floating-Point Available */
160	#define PPC_MSR_ME (1 << 12) /* Machine Check Interrupt Enable */
161	#define PPC_MSR_FE0 (1 << 11) /* Floating-Point Exception Mode 0 */
162	#define PPC_MSR_SE (1 << 10) /* Single-Step Trace Enable */
163	#define PPC_MSR_BE (1 << 9) /* Branch Trace Enable */
164	#define PPC_MSR_FE1 (1 << 8) /* Floating-Point Exception Mode 1 */
165	#define PPC_MSR_IP (1 << 6) /* Vector Table at 0xfff00000 */
166	#define PPC_MSR_IR (1 << 5) /* Instruction Relocate */
167	#define PPC_MSR_DR (1 << 4) /* Data Relocate */
168	#define PPC_MSR_PMM (1 << 2) /* Performance Monitor Mark */
169	#define PPC_MSR_RI (1 << 1) /* Recoverable Interrupt */
170	#define PPC_MSR_LE (1) /* Little-Endian Mode */
171
172	/* Floating-point Status: */
173	#define PPC_FPSCR_FX (1 << 31) /* Exception summary */
174	#define PPC_FPSCR_FEX (1 << 30) /* Enabled Exception summary */
175	#define PPC_FPSCR_VX (1 << 29) /* Invalid Operation summary */
176	/* .. TODO */
177	#define PPC_FPSCR_VXNAN (1 << 24)
178	/* .. TODO */
179	#define PPC_FPSCR_FPCC 0x0000f000
180	#define PPC_FPSCR_FPCC_SHIFT 12
181	#define PPC_FPSCR_FL (1 << 15) /* Less than */
182	#define PPC_FPSCR_FG (1 << 14) /* Greater than */
183	#define PPC_FPSCR_FE (1 << 13) /* Equal or Zero */
184	#define PPC_FPSCR_FU (1 << 12) /* Unordered or NaN */
185
186	/* Exceptions: */
187	#define PPC_EXCEPTION_DSI 0x3 /* Data Storage Interrupt */
188	#define PPC_EXCEPTION_ISI 0x4 /* Instruction Storage Interrupt */
189	#define PPC_EXCEPTION_EI 0x5 /* External interrupt */
190	#define PPC_EXCEPTION_FPU 0x8 /* Floating-Point unavailable */
191	#define PPC_EXCEPTION_DEC 0x9 /* Decrementer */
192	#define PPC_EXCEPTION_SC 0xc /* Syscall */
193
194	/* XER bits: */
195	#define PPC_XER_SO (1UL << 31) /* Summary Overflow */
196	#define PPC_XER_OV (1 << 30) /* Overflow */
197	#define PPC_XER_CA (1 << 29) /* Carry */
198
199
200	/* cpu_ppc.c: */
201	int ppc_run_instr(struct cpu *cpu);
202	int ppc32_run_instr(struct cpu *cpu);
203	void ppc_exception(struct cpu *cpu, int exception_nr);
204	void ppc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
205	unsigned char *host_page, int writeflag, uint64_t paddr_page);
206	void ppc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
207	unsigned char *host_page, int writeflag, uint64_t paddr_page);
208	void ppc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
209	void ppc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
210	void ppc_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
211	void ppc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
212	void ppc_init_64bit_dummy_tables(struct cpu *cpu);
213	int ppc_memory_rw(struct cpu cpu, struct memory mem, uint64_t vaddr,
214	unsigned char *data, size_t len, int writeflag, int cache_flags);
215	int ppc_cpu_family_init(struct cpu_family *);
216
217	/* memory_ppc.c: */
218	int ppc_translate_v2p(struct cpu *cpu, uint64_t vaddr,
219	uint64_t *return_addr, int flags);
220
221	#endif /* CPU_PPC_H */