/[gxemul]/trunk/src/include/cpu_ppc.h
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Contents of /trunk/src/include/cpu_ppc.h

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Revision 12 - (show annotations)
Mon Oct 8 16:18:38 2007 UTC (12 years, 2 months ago) by dpavlin
File MIME type: text/plain
File size: 7159 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.905 2005/08/16 09:16:24 debug Exp $
20050628	Continuing the work on the ARM translation engine. end_of_page
		works. Experimenting with load/store translation caches
		(virtual -> physical -> host).
20050629	More ARM stuff (memory access translation cache, mostly). This
		might break a lot of stuff elsewhere, probably some MIPS-
		related translation things.
20050630	Many load/stores are now automatically generated and included
		into cpu_arm_instr.c; 1024 functions in total (!).
		Fixes based on feedback from Alec Voropay: only print 8 hex
		digits instead of 16 in some cases when emulating 32-bit
		machines; similar 8 vs 16 digit fix for breakpoint addresses;
		4Kc has 16 TLB entries, not 48; the MIPS config select1
		register is now printed with "reg ,0".
		Also changing many other occurances of 16 vs 8 digit output.
		Adding cache associativity fields to mips_cpu_types.h; updating
		some other cache fields; making the output of
		mips_cpu_dumpinfo() look nicer.
		Generalizing the bintrans stuff for device accesses to also
		work with the new translation system. (This might also break
		some MIPS things.)
		Adding multi-load/store instructions to the ARM disassembler
		and the translator, and some optimizations of various kinds.
20050701	Adding a simple dev_disk (it can read/write sectors from
		disk images).
20050712	Adding dev_ether (a simple ethernet send/receive device).
		Debugger command "ninstrs" for toggling show_nr_of_instructions
		during runtime.
		Removing the framebuffer logo.
20050713	Continuing on dev_ether.
		Adding a dummy cpu_alpha (again).
20050714	More work on cpu_alpha.
20050715	More work on cpu_alpha. Many instructions work, enough to run
		a simple framebuffer fill test (similar to the ARM test).
20050716	More Alpha stuff.
20050717	Minor updates (Alpha stuff).
20050718	Minor updates (Alpha stuff).
20050719	Generalizing some Alpha instructions.
20050720	More Alpha-related updates.
20050721	Continuing on cpu_alpha. Importing rpb.h from NetBSD/alpha.
20050722	Alpha-related updates: userland stuff (Hello World using
		write() compiled statically for FreeBSD/Alpha runs fine), and
		more instructions are now implemented.
20050723	Fixing ldq_u and stq_u.
		Adding more instructions (conditional moves, masks, extracts,
		shifts).
20050724	More FreeBSD/Alpha userland stuff, and adding some more
		instructions (inserts).
20050725	Continuing on the Alpha stuff. (Adding dummy ldt/stt.)
		Adding a -A command line option to turn off alignment checks
		in some cases (for translated code).
		Trying to remove the old bintrans code which updated the pc
		and nr_of_executed_instructions for every instruction.
20050726	Making another attempt att removing the pc/nr of instructions
		code. This time it worked, huge performance increase for
		artificial test code, but performance loss for real-world
		code :-( so I'm scrapping that code for now.
		Tiny performance increase on Alpha (by using ret instead of
		jmp, to play nice with the Alpha's branch prediction) for the
		old MIPS bintrans backend.
20050727	Various minor fixes and cleanups.
20050728	Switching from a 2-level virtual to host/physical translation
		system for ARM emulation, to a 1-level translation.
		Trying to switch from 2-level to 1-level for the MIPS bintrans
		system as well (Alpha only, so far), but there is at least one
		problem: caches and/or how they work with device mappings.
20050730	Doing the 2-level to 1-level conversion for the i386 backend.
		The cache/device bug is still there for R2K/3K :(
		Various other minor updates (Malta etc).
		The mc146818 clock now updates the UIP bit in a way which works
		better with Linux for at least sgimips and Malta emulation.
		Beginning the work on refactoring the dyntrans system.
20050731	Continuing the dyntrans refactoring.
		Fixing a small but serious host alignment bug in memory_rw.
		Adding support for big-endian load/stores to the i386 bintrans
		backend.
		Another minor i386 bintrans backend update: stores from the
		zero register are now one (or two) loads shorter.
		The slt and sltu instructions were incorrectly implemented for
		the i386 backend; only using them for 32-bit mode for now.
20050801	Continuing the dyntrans refactoring.
		Cleanup of the ns16550 serial controller (removing unnecessary
		code).
		Bugfix (memory corruption bug) in dev_gt, and a patch/hack from
		Alec Voropay for Linux/Malta.
20050802	More cleanup/refactoring of the dyntrans subsystem: adding
		phys_page pointers to the lookup tables, for quick jumps
		between translated pages.
		Better fix for the ns16550 device (but still no real FIFO
		functionality).
		Converting cpu_ppc to the new dyntrans system. This means that
		I will have to start from scratch with implementing each
		instruction, and figure out how to implement dual 64/32-bit
		modes etc.
		Removing the URISC CPU family, because it was useless.
20050803	When selecting a machine type, the main type can now be omitted
		if the subtype name is unique. (I.e. -E can be omitted.)
		Fixing a dyntrans/device update bug. (Writes to offset 0 of
		a device could sometimes go unnoticed.)
		Adding an experimental "instruction combination" hack for
		ARM for memset-like byte fill loops.
20050804	Minor progress on cpu_alpha and related things.
		Finally fixing the MIPS dmult/dmultu bugs.
		Fixing some minor TODOs.
20050805	Generalizing the 8259 PIC. It now also works with Cobalt
		and evbmips emulation, in addition to the x86 hack.
		Finally converting the ns16550 device to use devinit.
		Continuing the work on the dyntrans system. Thinking about
		how to add breakpoints.
20050806	More dyntrans updates. Breakpoints seem to work now.
20050807	Minor updates: cpu_alpha and related things; removing
		dev_malta (as it isn't used any more).
		Dyntrans: working on general "show trace tree" support.
		The trace tree stuff now works with both the old MIPS code and
		with newer dyntrans modes. :)
		Continuing on Alpha-related stuff (trying to get *BSD to boot
		a bit further, adding more instructions, etc).
20050808	Adding a dummy IA64 cpu family, and continuing the refactoring
		of the dyntrans system.
		Removing the regression test stuff, because it was more or
		less useless.
		Adding loadlinked/storeconditional type instructions to the
		Alpha emulation. (Needed for Linux/alpha. Not very well tested
		yet.)
20050809	The function call trace tree now prints a per-function nr of
		arguments. (Semi-meaningless, since that data isn't read yet
		from the ELFs; some hardcoded symbols such as memcpy() and
		strlen() work fine, though.)
		More dyntrans refactoring; taking out more of the things that
		are common to all cpu families.
20050810	Working on adding support for "dual mode" for PPC dyntrans
		(i.e. both 64-bit and 32-bit modes).
		(Re)adding some simple PPC instructions.
20050811	Adding a dummy M68K cpu family. The dyntrans system isn't ready
		for variable-length ISAs yet, so it's completely bogus so far.
		Re-adding more PPC instructions.
		Adding a hack to src/file.c which allows OpenBSD/mac68k a.out
		kernels to be loaded.
		Beginning to add PPC loads/stores. So far they only work in
		32-bit mode.
20050812	The configure file option "add_remote" now accepts symbolic
		host names, in addition to numeric IPv4 addresses.
		Re-adding more PPC instructions.
20050814	Continuing to port back more PPC instructions.
		Found and fixed the cache/device write-update bug for 32-bit
		MIPS bintrans. :-)
		Triggered a really weird and annoying bug in Compaq's C
		compiler; ccc sometimes outputs code which loads from an
		address _before_ checking whether the pointer was NULL or not.
		(I'm not sure how to handle this problem.)
20050815	Removing all of the old x86 instruction execution code; adding
		a new (dummy) dyntrans module for x86.
		Taking the first steps to extend the dyntrans system to support
		variable-length instructions.
		Slowly preparing for the next release.
20050816	Adding a dummy SPARC cpu module.
		Minor updates (documentation etc) for the release.

==============  RELEASE 0.3.5  ==============


1 #ifndef CPU_PPC_H
2 #define CPU_PPC_H
3
4 /*
5 * Copyright (C) 2005 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cpu_ppc.h,v 1.29 2005/08/14 23:44:23 debug Exp $
32 */
33
34 #include "misc.h"
35
36
37 struct cpu_family;
38
39 #define MODE_PPC 0
40 #define MODE_POWER 1
41
42 /* PPC CPU types: */
43 struct ppc_cpu_type_def {
44 char *name;
45 int bits;
46 int flags;
47 int icache_shift;
48 int iway;
49 int dcache_shift;
50 int dway;
51 int l2cache_shift;
52 int l2way;
53 int altivec;
54
55 /* TODO: POWER vs PowerPC? */
56 };
57
58 /* Flags: */
59 #define PPC_NOFP 1
60 /* TODO: Most of these just bogus */
61
62 #define PPC_CPU_TYPE_DEFS { \
63 { "PPC405GP", 32, PPC_NOFP, 15, 2, 15, 2, 20, 1, 0 }, \
64 { "PPC603e", 32, 0, 14, 4, 14, 4, 0, 0, 0 }, \
65 { "MPC7400", 32, 0, 15, 2, 15, 2, 19, 1, 1 }, \
66 { "PPC750", 32, 0, 15, 2, 15, 2, 20, 1, 0 }, \
67 { "G4e", 32, 0, 15, 8, 15, 8, 18, 8, 1 }, \
68 { "PPC970", 64, 0, 16, 1, 15, 2, 19, 1, 1 }, \
69 { NULL, 0, 0, 0,0, 0,0, 0,0, 0 } \
70 };
71
72 #define PPC_NGPRS 32
73 #define PPC_NFPRS 32
74
75
76 #define PPC_N_IC_ARGS 3
77 #define PPC_INSTR_ALIGNMENT_SHIFT 2
78 #define PPC_IC_ENTRIES_SHIFT 10
79 #define PPC_IC_ENTRIES_PER_PAGE (1 << PPC_IC_ENTRIES_SHIFT)
80 #define PPC_PC_TO_IC_ENTRY(a) (((a)>>PPC_INSTR_ALIGNMENT_SHIFT) \
81 & (PPC_IC_ENTRIES_PER_PAGE-1))
82 #define PPC_ADDR_TO_PAGENR(a) ((a) >> (PPC_IC_ENTRIES_SHIFT \
83 + PPC_INSTR_ALIGNMENT_SHIFT))
84
85 struct ppc_instr_call {
86 void (*f)(struct cpu *, struct ppc_instr_call *);
87 size_t arg[PPC_N_IC_ARGS];
88 };
89
90 /* Translation cache struct for each physical page: */
91 struct ppc_tc_physpage {
92 uint32_t next_ofs; /* or 0 for end of chain */
93 uint64_t physaddr;
94 int flags;
95 struct ppc_instr_call ics[PPC_IC_ENTRIES_PER_PAGE + 1];
96 };
97
98 #define PPC_N_VPH_ENTRIES 1048576
99
100 #define PPC_MAX_VPH_TLB_ENTRIES 256
101 struct ppc_vpg_tlb_entry {
102 int valid;
103 int writeflag;
104 int64_t timestamp;
105 unsigned char *host_page;
106 uint64_t vaddr_page;
107 uint64_t paddr_page;
108 };
109
110 struct ppc_cpu {
111 struct ppc_cpu_type_def cpu_type;
112
113 uint64_t of_emul_addr;
114 uint64_t pc_last;
115
116 int mode; /* MODE_PPC or MODE_POWER */
117 int bits; /* 32 or 64 */
118
119 uint64_t zero; /* A zero register */
120
121 uint32_t cr; /* Condition Register */
122 uint32_t fpscr; /* FP Status and Control Register */
123 uint64_t lr; /* Link Register */
124 uint64_t ctr; /* Count Register */
125 uint64_t gpr[PPC_NGPRS]; /* General Purpose Registers */
126 uint64_t xer; /* FP Exception Register */
127 uint64_t fpr[PPC_NFPRS]; /* Floating-Point Registers */
128
129 uint32_t tbl; /* Time Base Lower */
130 uint32_t tbu; /* Time Base Upper */
131 uint32_t dec; /* Decrementer */
132 uint32_t hdec; /* Hypervisor Decrementer */
133 uint64_t ssr0; /* Machine status save/restore
134 register 0 */
135 uint64_t ssr1; /* Machine status save/restore
136 register 1 */
137 uint64_t msr; /* Machine state register */
138 uint64_t sprg0; /* Special Purpose Register G0 */
139 uint64_t sprg1; /* Special Purpose Register G1 */
140 uint64_t sprg2; /* Special Purpose Register G2 */
141 uint64_t sprg3; /* Special Purpose Register G3 */
142 uint32_t pvr; /* Processor Version Register */
143 uint32_t pir; /* Processor ID */
144
145
146 /*
147 * Instruction translation cache:
148 */
149
150 /* cur_ic_page is a pointer to an array of PPC_IC_ENTRIES_PER_PAGE
151 instruction call entries. next_ic points to the next such
152 call to be executed. */
153 struct ppc_tc_physpage *cur_physpage;
154 struct ppc_instr_call *cur_ic_page;
155 struct ppc_instr_call *next_ic;
156
157
158 /*
159 * Virtual -> physical -> host address translation:
160 *
161 * host_load and host_store point to arrays of PPC_N_VPH_ENTRIES
162 * pointers (to host pages); phys_addr points to an array of
163 * PPC_N_VPH_ENTRIES uint32_t.
164 */
165
166 struct ppc_vpg_tlb_entry vph_tlb_entry[PPC_MAX_VPH_TLB_ENTRIES];
167 unsigned char *host_load[PPC_N_VPH_ENTRIES];
168 unsigned char *host_store[PPC_N_VPH_ENTRIES];
169 uint32_t phys_addr[PPC_N_VPH_ENTRIES];
170 struct ppc_tc_physpage *phys_page[PPC_N_VPH_ENTRIES];
171 };
172
173
174 /* Machine status word bits: (according to Book 3) */
175 #define PPC_MSR_SF (1ULL << 63) /* Sixty-Four-Bit Mode */
176 /* bits 62..61 are reserved */
177 #define PPC_MSR_HV (1ULL << 60) /* Hypervisor */
178 /* bits 59..17 are reserved */
179 #define PPC_MSR_ILE (1 << 16) /* Interrupt Little-Endian Mode */
180 #define PPC_MSR_EE (1 << 15) /* External Interrupt Enable */
181 #define PPC_MSR_PR (1 << 14) /* Problem State */
182 #define PPC_MSR_FP (1 << 13) /* Floating-Point Available */
183 #define PPC_MSR_ME (1 << 12) /* Machine Check Interrupt Enable */
184 #define PPC_MSR_FE0 (1 << 11) /* Floating-Point Exception Mode 0 */
185 #define PPC_MSR_SE (1 << 10) /* Single-Step Trace Enable */
186 #define PPC_MSR_BE (1 << 9) /* Branch Trace Enable */
187 #define PPC_MSR_FE1 (1 << 8) /* Floating-Point Exception Mode 1 */
188 #define PPC_MSR_IR (1 << 5) /* Instruction Relocate */
189 #define PPC_MSR_DR (1 << 4) /* Data Relocate */
190 #define PPC_MSR_PMM (1 << 2) /* Performance Monitor Mark */
191 #define PPC_MSR_RI (1 << 1) /* Recoverable Interrupt */
192 #define PPC_MSR_LE (1) /* Little-Endian Mode */
193
194 /* XER bits: */
195 #define PPC_XER_SO (1 << 31) /* Summary Overflow */
196 #define PPC_XER_OV (1 << 30) /* Overflow */
197 #define PPC_XER_CA (1 << 29) /* Carry */
198
199
200 /* cpu_ppc.c: */
201 void ppc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
202 unsigned char *host_page, int writeflag, uint64_t paddr_page);
203 void ppc_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t paddr);
204 void ppc_invalidate_code_translation_caches(struct cpu *cpu);
205 int ppc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
206 unsigned char *data, size_t len, int writeflag, int cache_flags);
207 int ppc_cpu_family_init(struct cpu_family *);
208
209
210 #endif /* CPU_PPC_H */

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