/[gxemul]/trunk/src/include/cpu_ppc.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 20 by dpavlin, Mon Oct 8 16:19:23 2007 UTC revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC
# Line 2  Line 2 
2  #define CPU_PPC_H  #define CPU_PPC_H
3    
4  /*  /*
5   *  Copyright (C) 2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_ppc.h,v 1.55 2005/11/24 01:15:07 debug Exp $   *  $Id: cpu_ppc.h,v 1.60 2006/02/09 22:40:27 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
# Line 63  struct ppc_cpu_type_def { Line 63  struct ppc_cpu_type_def {
63  #define PPC_NOFP                1  #define PPC_NOFP                1
64  #define PPC_601                 2  #define PPC_601                 2
65  #define PPC_603                 4  #define PPC_603                 4
66    #define PPC_NO_DEC              8       /*  No DEC (decrementer) SPR  */
67    
68  /*  TODO: Most of these just bogus  */  /*  TODO: Most of these just bogus  */
69    
70  #define PPC_CPU_TYPE_DEFS       {                                       \  #define PPC_CPU_TYPE_DEFS       {                                       \
71          { "PPC405GP",   0,          32, PPC_NOFP, 15,5,2, 15,5,2, 20,5,1, 0 }, \          { "PPC405GP",   0x40110000, 32, PPC_NOFP|PPC_NO_DEC,            \
72          { "PPC601",     0,          32, PPC_601, 14,5,4, 14,5,4, 0,0,0, 0 },    \                                          13,5,2, 13,5,2, 0,5,1, 0 },     \
73          { "PPC603",     0x00030302, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 },    \          { "PPC601",     0,          32, PPC_601, 14,5,4, 14,5,4, 0,0,0, 0 },\
74          { "PPC603e",    0x00060104, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 },    \          { "PPC603",     0x00030302, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 },\
75            { "PPC603e",    0x00060104, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 },\
76          { "PPC604",     0x00040304, 32, 0, 15,5,4, 15,5,4, 0,0,0, 0 },  \          { "PPC604",     0x00040304, 32, 0, 15,5,4, 15,5,4, 0,0,0, 0 },  \
77          { "PPC620",     0x00140000, 64, 0, 15,5,4, 15,5,4, 0,0,0, 0 },  \          { "PPC620",     0x00140000, 64, 0, 15,5,4, 15,5,4, 0,0,0, 0 },  \
78          { "MPC7400",    0x000c0000, 32, 0, 15,5,2, 15,5,2, 19,5,1, 1 }, \          { "MPC7400",    0x000c0000, 32, 0, 15,5,2, 15,5,2, 19,5,1, 1 }, \
# Line 92  struct ppc_cpu_type_def { Line 95  struct ppc_cpu_type_def {
95  #define PPC_ADDR_TO_PAGENR(a)           ((a) >> (PPC_IC_ENTRIES_SHIFT \  #define PPC_ADDR_TO_PAGENR(a)           ((a) >> (PPC_IC_ENTRIES_SHIFT \
96                                          + PPC_INSTR_ALIGNMENT_SHIFT))                                          + PPC_INSTR_ALIGNMENT_SHIFT))
97    
98  struct ppc_instr_call {  DYNTRANS_MISC_DECLARATIONS(ppc,PPC,uint64_t)
         void    (*f)(struct cpu *, struct ppc_instr_call *);  
         size_t  arg[PPC_N_IC_ARGS];  
 };  
   
 /*  Translation cache struct for each physical page:  */  
 struct ppc_tc_physpage {  
         struct ppc_instr_call ics[PPC_IC_ENTRIES_PER_PAGE + 1];  
         uint32_t        next_ofs;       /*  or 0 for end of chain  */  
         int             flags;  
         uint64_t        physaddr;  
 };  
   
 #define PPC_N_VPH_ENTRIES               1048576  
99    
100  #define PPC_MAX_VPH_TLB_ENTRIES         128  #define PPC_MAX_VPH_TLB_ENTRIES         128
101  struct ppc_vpg_tlb_entry {  
         uint8_t         valid;  
         uint8_t         writeflag;  
         int64_t         timestamp;  
         uint64_t        vaddr_page;  
         uint64_t        paddr_page;  
         unsigned char   *host_page;  
 };  
102    
103  struct ppc_cpu {  struct ppc_cpu {
104          struct ppc_cpu_type_def cpu_type;          struct ppc_cpu_type_def cpu_type;
# Line 145  struct ppc_cpu { Line 128  struct ppc_cpu {
128    
129    
130          /*          /*
131           *  Instruction translation cache:           *  Instruction translation cache and Virtual->Physical->Host
132             *  address translation:
133           */           */
134            DYNTRANS_ITC(ppc)
135          /*  cur_ic_page is a pointer to an array of PPC_IC_ENTRIES_PER_PAGE          VPH_TLBS(ppc,PPC)
136              instruction call entries. next_ic points to the next such          VPH32(ppc,PPC,uint64_t,uint8_t)
137              call to be executed.  */          VPH64(ppc,PPC,uint8_t)
         struct ppc_tc_physpage  *cur_physpage;  
         struct ppc_instr_call   *cur_ic_page;  
         struct ppc_instr_call   *next_ic;  
   
         void                    (*combination_check)(struct cpu *,  
                                     struct ppc_instr_call *, int low_addr);  
   
         /*  
          *  Virtual -> physical -> host address translation:  
          *  
          *  host_load and host_store point to arrays of PPC_N_VPH_ENTRIES  
          *  pointers (to host pages); phys_addr points to an array of  
          *  PPC_N_VPH_ENTRIES uint32_t.  
          */  
   
         struct ppc_vpg_tlb_entry        vph_tlb_entry[PPC_MAX_VPH_TLB_ENTRIES];  
         unsigned char                   *host_load[PPC_N_VPH_ENTRIES];  
         unsigned char                   *host_store[PPC_N_VPH_ENTRIES];  
         uint32_t                        phys_addr[PPC_N_VPH_ENTRIES];  
         struct ppc_tc_physpage          *phys_page[PPC_N_VPH_ENTRIES];  
   
         uint32_t                        phystranslation[PPC_N_VPH_ENTRIES/32];  
         uint8_t                         vaddr_to_tlbindex[PPC_N_VPH_ENTRIES];  
138  };  };
139    
140    
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