28 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
29 |
* |
* |
30 |
* |
* |
31 |
* $Id: cpu_ppc.h,v 1.41 2005/10/27 14:01:15 debug Exp $ |
* $Id: cpu_ppc.h,v 1.55 2005/11/24 01:15:07 debug Exp $ |
32 |
*/ |
*/ |
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#include "misc.h" |
#include "misc.h" |
61 |
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62 |
/* Flags: */ |
/* Flags: */ |
63 |
#define PPC_NOFP 1 |
#define PPC_NOFP 1 |
64 |
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#define PPC_601 2 |
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#define PPC_603 4 |
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/* TODO: Most of these just bogus */ |
/* TODO: Most of these just bogus */ |
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68 |
#define PPC_CPU_TYPE_DEFS { \ |
#define PPC_CPU_TYPE_DEFS { \ |
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{ "PPC405GP", 0, 32, PPC_NOFP, 15,5,2, 15,5,2, 20,5,1, 0 }, \ |
{ "PPC405GP", 0, 32, PPC_NOFP, 15,5,2, 15,5,2, 20,5,1, 0 }, \ |
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{ "PPC603e", 0, 32, 0, 14,5,4, 14,5,4, 0,0,0, 0 }, \ |
{ "PPC601", 0, 32, PPC_601, 14,5,4, 14,5,4, 0,0,0, 0 }, \ |
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{ "PPC603", 0x00030302, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 }, \ |
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{ "PPC603e", 0x00060104, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 }, \ |
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{ "PPC604", 0x00040304, 32, 0, 15,5,4, 15,5,4, 0,0,0, 0 }, \ |
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{ "PPC620", 0x00140000, 64, 0, 15,5,4, 15,5,4, 0,0,0, 0 }, \ |
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{ "MPC7400", 0x000c0000, 32, 0, 15,5,2, 15,5,2, 19,5,1, 1 }, \ |
{ "MPC7400", 0x000c0000, 32, 0, 15,5,2, 15,5,2, 19,5,1, 1 }, \ |
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{ "PPC750", 0x00084202, 32, 0, 15,5,2, 15,5,2, 20,5,1, 0 }, \ |
{ "PPC750", 0x00084202, 32, 0, 15,5,2, 15,5,2, 20,5,1, 0 }, \ |
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{ "G4e", 0, 32, 0, 15,5,8, 15,5,8, 18,5,8, 1 }, \ |
{ "G4e", 0, 32, 0, 15,5,8, 15,5,8, 18,5,8, 1 }, \ |
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#define PPC_NGPRS 32 |
#define PPC_NGPRS 32 |
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#define PPC_NFPRS 32 |
#define PPC_NFPRS 32 |
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#define PPC_N_TGPRS 4 |
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86 |
#define PPC_N_IC_ARGS 3 |
#define PPC_N_IC_ARGS 3 |
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#define PPC_INSTR_ALIGNMENT_SHIFT 2 |
#define PPC_INSTR_ALIGNMENT_SHIFT 2 |
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#define PPC_N_VPH_ENTRIES 1048576 |
#define PPC_N_VPH_ENTRIES 1048576 |
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#define PPC_MAX_VPH_TLB_ENTRIES 256 |
#define PPC_MAX_VPH_TLB_ENTRIES 128 |
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struct ppc_vpg_tlb_entry { |
struct ppc_vpg_tlb_entry { |
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int valid; |
uint8_t valid; |
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int writeflag; |
uint8_t writeflag; |
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int64_t timestamp; |
int64_t timestamp; |
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unsigned char *host_page; |
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uint64_t vaddr_page; |
uint64_t vaddr_page; |
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uint64_t paddr_page; |
uint64_t paddr_page; |
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unsigned char *host_page; |
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}; |
}; |
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struct ppc_cpu { |
struct ppc_cpu { |
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int mode; /* MODE_PPC or MODE_POWER */ |
int mode; /* MODE_PPC or MODE_POWER */ |
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int bits; /* 32 or 64 */ |
int bits; /* 32 or 64 */ |
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128 |
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int irq_asserted; /* External Interrupt flag */ |
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int dec_intr_pending;/* Decrementer interrupt pending */ |
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uint64_t zero; /* A zero register */ |
uint64_t zero; /* A zero register */ |
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uint32_t cr; /* Condition Register */ |
uint32_t cr; /* Condition Register */ |
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uint32_t fpscr; /* FP Status and Control Register */ |
uint32_t fpscr; /* FP Status and Control Register */ |
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uint64_t lr; /* Link Register */ |
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uint64_t ctr; /* Count Register */ |
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uint64_t gpr[PPC_NGPRS]; /* General Purpose Registers */ |
uint64_t gpr[PPC_NGPRS]; /* General Purpose Registers */ |
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uint64_t xer; /* FP Exception Register */ |
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uint64_t fpr[PPC_NFPRS]; /* Floating-Point Registers */ |
uint64_t fpr[PPC_NFPRS]; /* Floating-Point Registers */ |
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uint32_t tbl; /* Time Base Lower */ |
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uint32_t tbu; /* Time Base Upper */ |
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uint32_t dec; /* Decrementer */ |
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uint32_t hdec; /* Hypervisor Decrementer */ |
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uint64_t sdr1; /* Storage Descriptor Register */ |
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uint64_t srr0; /* Supervisor save/restore 0 */ |
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uint64_t srr1; /* Supervisor save/restore 1 */ |
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uint64_t ssr0; /* Machine status save/restore |
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register 0 */ |
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uint64_t ssr1; /* Machine status save/restore |
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register 1 */ |
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137 |
uint64_t msr; /* Machine state register */ |
uint64_t msr; /* Machine state register */ |
138 |
uint64_t sprg0; /* Special Purpose Register G0 */ |
uint64_t tgpr[PPC_N_TGPRS];/*Temporary gpr 0..3 */ |
139 |
uint64_t sprg1; /* Special Purpose Register G1 */ |
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140 |
uint64_t sprg2; /* Special Purpose Register G2 */ |
uint32_t sr[16]; /* Segment registers. */ |
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uint64_t sprg3; /* Special Purpose Register G3 */ |
uint64_t spr[1024]; |
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uint64_t dbsr; /* Debug Status Register */ |
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uint32_t pvr; /* Processor Version Register */ |
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uint32_t pir; /* Processor ID */ |
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/* TODO: 64-bit SRs? (Segment registers) */ |
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uint32_t sr[16]; |
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/* TODO: 64-bit BATs? */ |
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uint32_t ibat_u[4]; |
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uint32_t ibat_l[4]; |
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uint32_t dbat_u[4]; |
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uint32_t dbat_l[4]; |
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142 |
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uint64_t ll_addr; /* Load-linked / store-conditional */ |
uint64_t ll_addr; /* Load-linked / store-conditional */ |
144 |
int ll_bit; |
int ll_bit; |
155 |
struct ppc_instr_call *cur_ic_page; |
struct ppc_instr_call *cur_ic_page; |
156 |
struct ppc_instr_call *next_ic; |
struct ppc_instr_call *next_ic; |
157 |
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158 |
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void (*combination_check)(struct cpu *, |
159 |
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struct ppc_instr_call *, int low_addr); |
160 |
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161 |
/* |
/* |
162 |
* Virtual -> physical -> host address translation: |
* Virtual -> physical -> host address translation: |
173 |
struct ppc_tc_physpage *phys_page[PPC_N_VPH_ENTRIES]; |
struct ppc_tc_physpage *phys_page[PPC_N_VPH_ENTRIES]; |
174 |
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175 |
uint32_t phystranslation[PPC_N_VPH_ENTRIES/32]; |
uint32_t phystranslation[PPC_N_VPH_ENTRIES/32]; |
176 |
int16_t vaddr_to_tlbindex[PPC_N_VPH_ENTRIES]; |
uint8_t vaddr_to_tlbindex[PPC_N_VPH_ENTRIES]; |
177 |
}; |
}; |
178 |
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179 |
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182 |
/* bits 62..61 are reserved */ |
/* bits 62..61 are reserved */ |
183 |
#define PPC_MSR_HV (1ULL << 60) /* Hypervisor */ |
#define PPC_MSR_HV (1ULL << 60) /* Hypervisor */ |
184 |
/* bits 59..17 are reserved */ |
/* bits 59..17 are reserved */ |
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#define PPC_MSR_VEC (1 << 25) /* Altivec Enable */ |
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#define PPC_MSR_TGPR (1 << 17) /* Temporary gpr0..3 */ |
187 |
#define PPC_MSR_ILE (1 << 16) /* Interrupt Little-Endian Mode */ |
#define PPC_MSR_ILE (1 << 16) /* Interrupt Little-Endian Mode */ |
188 |
#define PPC_MSR_EE (1 << 15) /* External Interrupt Enable */ |
#define PPC_MSR_EE (1 << 15) /* External Interrupt Enable */ |
189 |
#define PPC_MSR_PR (1 << 14) /* Problem State */ |
#define PPC_MSR_PR (1 << 14) /* Problem/Privilege State */ |
190 |
#define PPC_MSR_FP (1 << 13) /* Floating-Point Available */ |
#define PPC_MSR_FP (1 << 13) /* Floating-Point Available */ |
191 |
#define PPC_MSR_ME (1 << 12) /* Machine Check Interrupt Enable */ |
#define PPC_MSR_ME (1 << 12) /* Machine Check Interrupt Enable */ |
192 |
#define PPC_MSR_FE0 (1 << 11) /* Floating-Point Exception Mode 0 */ |
#define PPC_MSR_FE0 (1 << 11) /* Floating-Point Exception Mode 0 */ |
193 |
#define PPC_MSR_SE (1 << 10) /* Single-Step Trace Enable */ |
#define PPC_MSR_SE (1 << 10) /* Single-Step Trace Enable */ |
194 |
#define PPC_MSR_BE (1 << 9) /* Branch Trace Enable */ |
#define PPC_MSR_BE (1 << 9) /* Branch Trace Enable */ |
195 |
#define PPC_MSR_FE1 (1 << 8) /* Floating-Point Exception Mode 1 */ |
#define PPC_MSR_FE1 (1 << 8) /* Floating-Point Exception Mode 1 */ |
196 |
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#define PPC_MSR_IP (1 << 6) /* Vector Table at 0xfff00000 */ |
197 |
#define PPC_MSR_IR (1 << 5) /* Instruction Relocate */ |
#define PPC_MSR_IR (1 << 5) /* Instruction Relocate */ |
198 |
#define PPC_MSR_DR (1 << 4) /* Data Relocate */ |
#define PPC_MSR_DR (1 << 4) /* Data Relocate */ |
199 |
#define PPC_MSR_PMM (1 << 2) /* Performance Monitor Mark */ |
#define PPC_MSR_PMM (1 << 2) /* Performance Monitor Mark */ |
200 |
#define PPC_MSR_RI (1 << 1) /* Recoverable Interrupt */ |
#define PPC_MSR_RI (1 << 1) /* Recoverable Interrupt */ |
201 |
#define PPC_MSR_LE (1) /* Little-Endian Mode */ |
#define PPC_MSR_LE (1) /* Little-Endian Mode */ |
202 |
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203 |
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/* Floating-point Status: */ |
204 |
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#define PPC_FPSCR_FX (1 << 31) /* Exception summary */ |
205 |
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#define PPC_FPSCR_FEX (1 << 30) /* Enabled Exception summary */ |
206 |
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#define PPC_FPSCR_VX (1 << 29) /* Invalid Operation summary */ |
207 |
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/* .. TODO */ |
208 |
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#define PPC_FPSCR_VXNAN (1 << 24) |
209 |
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/* .. TODO */ |
210 |
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#define PPC_FPSCR_FPCC 0x0000f000 |
211 |
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#define PPC_FPSCR_FPCC_SHIFT 12 |
212 |
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#define PPC_FPSCR_FL (1 << 15) /* Less than */ |
213 |
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#define PPC_FPSCR_FG (1 << 14) /* Greater than */ |
214 |
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#define PPC_FPSCR_FE (1 << 13) /* Equal or Zero */ |
215 |
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#define PPC_FPSCR_FU (1 << 12) /* Unordered or NaN */ |
216 |
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217 |
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/* Exceptions: */ |
218 |
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#define PPC_EXCEPTION_DSI 0x3 /* Data Storage Interrupt */ |
219 |
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#define PPC_EXCEPTION_ISI 0x4 /* Instruction Storage Interrupt */ |
220 |
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#define PPC_EXCEPTION_EI 0x5 /* External interrupt */ |
221 |
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#define PPC_EXCEPTION_FPU 0x8 /* Floating-Point unavailable */ |
222 |
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#define PPC_EXCEPTION_DEC 0x9 /* Decrementer */ |
223 |
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#define PPC_EXCEPTION_SC 0xc /* Syscall */ |
224 |
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|
225 |
/* XER bits: */ |
/* XER bits: */ |
226 |
#define PPC_XER_SO (1UL << 31) /* Summary Overflow */ |
#define PPC_XER_SO (1UL << 31) /* Summary Overflow */ |
227 |
#define PPC_XER_OV (1 << 30) /* Overflow */ |
#define PPC_XER_OV (1 << 30) /* Overflow */ |
229 |
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230 |
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231 |
/* cpu_ppc.c: */ |
/* cpu_ppc.c: */ |
232 |
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void ppc_exception(struct cpu *cpu, int exception_nr); |
233 |
void ppc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
void ppc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
234 |
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
235 |
void ppc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
void ppc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |