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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_ppc.h,v 1.23 2005/06/26 22:23:43 debug Exp $ |
* $Id: cpu_ppc.h,v 1.38 2005/09/24 23:44:19 debug Exp $ |
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*/ |
*/ |
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#include "misc.h" |
#include "misc.h" |
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/* PPC CPU types: */ |
/* PPC CPU types: */ |
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struct ppc_cpu_type_def { |
struct ppc_cpu_type_def { |
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char *name; |
char *name; |
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int pvr; |
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int bits; |
int bits; |
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int flags; |
int flags; |
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int icache_shift; |
int icache_shift; |
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int ilinesize; |
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int iway; |
int iway; |
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int dcache_shift; |
int dcache_shift; |
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int dlinesize; |
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int dway; |
int dway; |
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int l2cache_shift; |
int l2cache_shift; |
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int l2linesize; |
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int l2way; |
int l2way; |
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int altivec; |
int altivec; |
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|
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#define PPC_NOFP 1 |
#define PPC_NOFP 1 |
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/* TODO: Most of these just bogus */ |
/* TODO: Most of these just bogus */ |
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|
|
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#define PPC_CPU_TYPE_DEFS { \ |
#define PPC_CPU_TYPE_DEFS { \ |
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{ "PPC405GP", 32, PPC_NOFP, 15, 2, 15, 2, 20, 1, 0 }, \ |
{ "PPC405GP", 0, 32, PPC_NOFP, 15,5,2, 15,5,2, 20,5,1, 0 }, \ |
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{ "PPC603e", 32, 0, 14, 4, 14, 4, 0, 0, 0 }, \ |
{ "PPC603e", 0, 32, 0, 14,5,4, 14,5,4, 0,0,0, 0 }, \ |
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{ "MPC7400", 32, 0, 15, 2, 15, 2, 19, 1, 1 }, \ |
{ "MPC7400", 0x000c0000, 32, 0, 15,5,2, 15,5,2, 19,5,1, 1 }, \ |
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{ "PPC750", 32, 0, 15, 2, 15, 2, 20, 1, 0 }, \ |
{ "PPC750", 0x00084202, 32, 0, 15,5,2, 15,5,2, 20,5,1, 0 }, \ |
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{ "G4e", 32, 0, 15, 8, 15, 8, 18, 8, 1 }, \ |
{ "G4e", 0, 32, 0, 15,5,8, 15,5,8, 18,5,8, 1 }, \ |
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{ "PPC970", 64, 0, 16, 1, 15, 2, 19, 1, 1 }, \ |
{ "PPC970", 0x00390000, 64, 0, 16,7,1, 15,7,2, 19,7,1, 1 }, \ |
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{ NULL, 0, 0, 0,0, 0,0, 0,0, 0 } \ |
{ NULL, 0, 0,0,0,0,0,0,0,0,0,0,0,0 } \ |
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}; |
} |
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|
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#define PPC_NGPRS 32 |
#define PPC_NGPRS 32 |
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#define PPC_NFPRS 32 |
#define PPC_NFPRS 32 |
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#define PPC_N_IC_ARGS 3 |
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#define PPC_INSTR_ALIGNMENT_SHIFT 2 |
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#define PPC_IC_ENTRIES_SHIFT 10 |
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#define PPC_IC_ENTRIES_PER_PAGE (1 << PPC_IC_ENTRIES_SHIFT) |
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#define PPC_PC_TO_IC_ENTRY(a) (((a)>>PPC_INSTR_ALIGNMENT_SHIFT) \ |
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& (PPC_IC_ENTRIES_PER_PAGE-1)) |
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#define PPC_ADDR_TO_PAGENR(a) ((a) >> (PPC_IC_ENTRIES_SHIFT \ |
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+ PPC_INSTR_ALIGNMENT_SHIFT)) |
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struct ppc_instr_call { |
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void (*f)(struct cpu *, struct ppc_instr_call *); |
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size_t arg[PPC_N_IC_ARGS]; |
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}; |
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/* Translation cache struct for each physical page: */ |
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struct ppc_tc_physpage { |
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uint32_t next_ofs; /* or 0 for end of chain */ |
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uint64_t physaddr; |
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int flags; |
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struct ppc_instr_call ics[PPC_IC_ENTRIES_PER_PAGE + 1]; |
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}; |
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#define PPC_N_VPH_ENTRIES 1048576 |
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#define PPC_MAX_VPH_TLB_ENTRIES 256 |
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struct ppc_vpg_tlb_entry { |
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int valid; |
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int writeflag; |
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int64_t timestamp; |
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unsigned char *host_page; |
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uint64_t vaddr_page; |
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uint64_t paddr_page; |
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}; |
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struct ppc_cpu { |
struct ppc_cpu { |
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struct ppc_cpu_type_def cpu_type; |
struct ppc_cpu_type_def cpu_type; |
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int trace_tree_depth; |
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uint64_t of_emul_addr; |
uint64_t of_emul_addr; |
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uint64_t pc_last; |
|
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int mode; /* MODE_PPC or MODE_POWER */ |
int mode; /* MODE_PPC or MODE_POWER */ |
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int bits; /* 32 or 64 */ |
int bits; /* 32 or 64 */ |
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uint64_t zero; /* A zero register */ |
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|
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uint32_t cr; /* Condition Register */ |
uint32_t cr; /* Condition Register */ |
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uint32_t fpscr; /* FP Status and Control Register */ |
uint32_t fpscr; /* FP Status and Control Register */ |
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uint64_t lr; /* Link Register */ |
uint64_t lr; /* Link Register */ |
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uint32_t tbu; /* Time Base Upper */ |
uint32_t tbu; /* Time Base Upper */ |
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uint32_t dec; /* Decrementer */ |
uint32_t dec; /* Decrementer */ |
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uint32_t hdec; /* Hypervisor Decrementer */ |
uint32_t hdec; /* Hypervisor Decrementer */ |
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uint64_t sdr1; /* Storage Descriptor Register */ |
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uint64_t srr0; /* Supervisor save/restore 0 */ |
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uint64_t srr1; /* Supervisor save/restore 1 */ |
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uint64_t ssr0; /* Machine status save/restore |
uint64_t ssr0; /* Machine status save/restore |
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register 0 */ |
register 0 */ |
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uint64_t ssr1; /* Machine status save/restore |
uint64_t ssr1; /* Machine status save/restore |
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uint64_t sprg1; /* Special Purpose Register G1 */ |
uint64_t sprg1; /* Special Purpose Register G1 */ |
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uint64_t sprg2; /* Special Purpose Register G2 */ |
uint64_t sprg2; /* Special Purpose Register G2 */ |
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uint64_t sprg3; /* Special Purpose Register G3 */ |
uint64_t sprg3; /* Special Purpose Register G3 */ |
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uint64_t dbsr; /* Debug Status Register */ |
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uint32_t pvr; /* Processor Version Register */ |
uint32_t pvr; /* Processor Version Register */ |
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uint32_t pir; /* Processor ID */ |
uint32_t pir; /* Processor ID */ |
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/* TODO: 64-bit SRs? (Segment registers) */ |
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uint32_t sr[16]; |
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/* TODO: 64-bit BATs? */ |
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uint32_t ibat_u[4]; |
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uint32_t ibat_l[4]; |
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uint32_t dbat_u[4]; |
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uint32_t dbat_l[4]; |
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uint64_t ll_addr; /* Load-linked / store-conditional */ |
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int ll_bit; |
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/* |
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* Instruction translation cache: |
167 |
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*/ |
168 |
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|
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/* cur_ic_page is a pointer to an array of PPC_IC_ENTRIES_PER_PAGE |
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instruction call entries. next_ic points to the next such |
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call to be executed. */ |
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struct ppc_tc_physpage *cur_physpage; |
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struct ppc_instr_call *cur_ic_page; |
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struct ppc_instr_call *next_ic; |
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/* |
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* Virtual -> physical -> host address translation: |
179 |
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* |
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* host_load and host_store point to arrays of PPC_N_VPH_ENTRIES |
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* pointers (to host pages); phys_addr points to an array of |
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* PPC_N_VPH_ENTRIES uint32_t. |
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*/ |
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struct ppc_vpg_tlb_entry vph_tlb_entry[PPC_MAX_VPH_TLB_ENTRIES]; |
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unsigned char *host_load[PPC_N_VPH_ENTRIES]; |
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unsigned char *host_store[PPC_N_VPH_ENTRIES]; |
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uint32_t phys_addr[PPC_N_VPH_ENTRIES]; |
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struct ppc_tc_physpage *phys_page[PPC_N_VPH_ENTRIES]; |
190 |
}; |
}; |
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|
219 |
/* cpu_ppc.c: */ |
/* cpu_ppc.c: */ |
220 |
void ppc_cpu_show_full_statistics(struct machine *m); |
void ppc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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void ppc_cpu_register_match(struct machine *m, char *name, |
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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int writeflag, uint64_t *valuep, int *match_register); |
void ppc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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void ppc_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs); |
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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int ppc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
void ppc_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int); |
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int running, uint64_t addr, int bintrans); |
void ppc32_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int); |
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int ppc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr); |
void ppc_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
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int ppc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr); |
void ppc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
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int ppc_cpu_run(struct emul *emul, struct machine *machine); |
|
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void ppc_cpu_dumpinfo(struct cpu *cpu); |
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void ppc_cpu_list_available_types(void); |
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int ppc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
int ppc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, int writeflag, int cache_flags); |
unsigned char *data, size_t len, int writeflag, int cache_flags); |
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int ppc_cpu_family_init(struct cpu_family *); |
int ppc_cpu_family_init(struct cpu_family *); |
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/* memory_ppc.c: */ |
233 |
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int ppc_translate_address(struct cpu *cpu, uint64_t vaddr, |
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uint64_t *return_addr, int flags); |
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#endif /* CPU_PPC_H */ |
#endif /* CPU_PPC_H */ |