Parent Directory | Revision Log
++ trunk/HISTORY (local) $Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $ 20061029 Changing usleep(1) calls in the debugger to usleep(10000) 20061107 Adding a new disk image option (-d o...) which sets the ISO9660 filesystem base offset; also making some other hacks to allow NetBSD/dreamcast and homebrew demos/games to boot directly from a filesystem image. Moving Dreamcast-specific stuff in the documentation to its own page (dreamcast.html). Adding a border to the Dreamcast PVR framebuffer. 20061108 Adding a -T command line option (again?), for halting the emulator on unimplemented memory accesses. 20061109 Continuing on various SH4 and Dreamcast related things. The emulator should now halt on more unimplemented device accesses, instead of just printing a warning, forcing me to actually implement missing stuff :) 20061111 Continuing on SH4 and Dreamcast stuff. Adding a bogus Landisk (SH4) machine mode. 20061112 Implementing some parts of the Dreamcast GDROM device. With some ugly hacks, NetBSD can (barely) mount an ISO image. 20061113 NetBSD/dreamcast now starts booting from the Live CD image, but crashes randomly quite early on in the boot process. 20061122 Beginning on a skeleton interrupt.h and interrupt.c for the new interrupt subsystem. 20061124 Continuing on the new interrupt system; taking the first steps to attempt to connect CPUs (SuperH and MIPS) and devices (dev_cons and SH4 timer interrupts) to it. Many things will probably break from now on. 20061125 Converting dev_ns16550, dev_8253 to the new interrupt system. Attempting to begin to convert the ISA bus. 20061130 Incorporating a patch from Brian Foley for the configure script, which checks for X11 libs in /usr/X11R6/lib64 (which is used on some Linux systems). 20061227 Adding a note in the man page about booting from Dreamcast CDROM images (i.e. that no external kernel is needed). 20061229 Continuing on the interrupt system rewrite: beginning to convert more devices, adding abort() calls for legacy interrupt system calls so that everything now _has_ to be rewritten! Almost all machine modes are now completely broken. 20061230 More progress on removing old interrupt code, mostly related to the ISA bus + devices, the LCA bus (on AlphaBook1), and the Footbridge bus (for CATS). And some minor PCI stuff. Connecting the ARM cpu to the new interrupt system. The CATS, NetWinder, and QEMU_MIPS machine modes now work with the new interrupt system :) 20061231 Connecting PowerPC CPUs to the new interrupt system. Making PReP machines (IBM 6050) work again. Beginning to convert the GT PCI controller (for e.g. Malta and Cobalt emulation). Some things work, but not everything. Updating Copyright notices for 2007. 20070101 Converting dev_kn02 from legacy style to devinit; the 3max machine mode now works with the new interrupt system :-] 20070105 Beginning to convert the SGI O2 machine to the new interrupt system; finally converting O2 (IP32) devices to devinit, etc. 20070106 Continuing on the interrupt system redesign/rewrite; KN01 (PMAX), KN230, and Dreamcast ASIC interrupts should work again, moving out stuff from machine.h and devices.h into the corresponding devices, beginning the rewrite of i80321 interrupts, etc. 20070107 Beginning on the rewrite of Eagle interrupt stuff (PReP, etc). 20070117 Beginning the rewrite of Algor (V3) interrupts (finally changing dev_v3 into devinit style). 20070118 Removing the "bus" registry concept from machine.h, because it was practically meaningless. Continuing on the rewrite of Algor V3 ISA interrupts. 20070121 More work on Algor interrupts; they are now working again, well enough to run NetBSD/algor. :-) 20070122 Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips can be installed using the new interrupt system :-) 20070123 Making the testmips mode work with the new interrupt system. 20070127 Beginning to convert DEC5800 devices to devinit, and to the new interrupt system. Converting Playstation 2 devices to devinit, and converting the interrupt system. Also fixing a severe bug: the interrupt mask register on Playstation 2 is bitwise _toggled_ on writes. 20070128 Removing the dummy NetGear machine mode and the 8250 device (which was only used by the NetGear machine). Beginning to convert the MacPPC GC (Grand Central) interrupt controller to the new interrupt system. Converting Jazz interrupts (PICA61 etc.) to the new interrupt system. NetBSD/arc can be installed again :-) Fixing the JAZZ timer (hardcoding it at 100 Hz, works with NetBSD and it is better than a completely dummy timer as it was before). Converting dev_mp to the new interrupt system, although I haven't had time to actually test it yet. Completely removing src/machines/interrupts.c, cpu_interrupt and cpu_interrupt_ack in src/cpu.c, and src/include/machine_interrupts.h! Adding fatal error messages + abort() in the few places that are left to fix. Converting dev_z8530 to the new interrupt system. FINALLY removing the md_int struct completely from the machine struct. SH4 fixes (adding a PADDR invalidation in the ITLB replacement code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs all the way to the login prompt, and can be interacted with :-) Converting the CPC700 controller (PCI and interrupt controller for PM/PPC) to the new interrupt system. 20070129 Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/ sgimips' and OpenBSD/sgi's ramdisk kernels can now be interacted with again. 20070130 Moving out the MIPS multi_lw and _sw instruction combinations so that they are auto-generated at compile time instead. 20070131 Adding detection of amd64/x86_64 hosts in the configure script, for doing initial experiments (again :-) with native code generation. Adding a -k command line option to set the size of the dyntrans cache, and a -B command line option to disable native code generation, even if GXemul was compiled with support for native code generation for the specific host CPU architecture. 20070201 Experimenting with a skeleton for native code generation. Changing the default behaviour, so that native code generation is now disabled by default, and has to be enabled by using -b on the command line. 20070202 Continuing the native code generation experiments. Making PCI interrupts work for Footbridge again. 20070203 More native code generation experiments. Removing most of the native code generation experimental code, it does not make sense to include any quick hacks like this. Minor cleanup/removal of some more legacy MIPS interrupt code. 20070204 Making i80321 interrupts work again (for NetBSD/evbarm etc.), and fixing the timer at 100 Hz. 20070206 Experimenting with removing the wdc interrupt slowness hack. 20070207 Lowering the number of dyntrans TLB entries for MIPS from 192 to 128, resulting in a minor speed improvement. Minor optimization to the code invalidation routine in cpu_dyntrans.c. 20070208 Increasing (experimentally) the nr of dyntrans instructions per loop from 60 to 120. 20070210 Commenting out (experimentally) the dyntrans_device_danger detection in memory_rw.c. Changing the testmips and baremips machines to use a revision 2 MIPS64 CPU by default, instead of revision 1. Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC files, the PC bios emulation, and the Olivetti M700 (ARC) and db64360 emulation modes. 20070211 Adding an "mp" demo to the demos directory, which tests the SMP functionality of the testmips machine. Fixing PReP interrupts some more. NetBSD/prep now boots again. 20070216 Adding a "nop workaround" for booting Mach/PMAX to the documentation; thanks to Artur Bujdoso for the values. Converting more of the MacPPC interrupt stuff to the new system. Beginning to convert BeBox interrupts to the new system. PPC603e should NOT have the PPC_NO_DEC flag! Removing it. Correcting BeBox clock speed (it was set to 100 in the NetBSD bootinfo block, but should be 33000000/4), allowing NetBSD to start without using the (incorrect) PPC_NO_DEC hack. 20070217 Implementing (slow) AltiVec vector loads and stores, allowing NetBSD/macppc to finally boot using the GENERIC kernel :-) Updating the documentation with install instructions for NetBSD/macppc. 20070218-19 Regression testing for the release. ============== RELEASE 0.4.4 ==============
1 | #ifndef CPU_PPC_H |
2 | #define CPU_PPC_H |
3 | |
4 | /* |
5 | * Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions are met: |
9 | * |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
15 | * 3. The name of the author may not be used to endorse or promote products |
16 | * derived from this software without specific prior written permission. |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
19 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
24 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
26 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
28 | * SUCH DAMAGE. |
29 | * |
30 | * |
31 | * $Id: cpu_ppc.h,v 1.69 2007/02/16 19:57:56 debug Exp $ |
32 | */ |
33 | |
34 | #include "misc.h" |
35 | |
36 | |
37 | struct cpu_family; |
38 | |
39 | #define MODE_PPC 0 |
40 | #define MODE_POWER 1 |
41 | |
42 | /* PPC CPU types: */ |
43 | struct ppc_cpu_type_def { |
44 | char *name; |
45 | int pvr; |
46 | int bits; |
47 | int flags; |
48 | int icache_shift; |
49 | int ilinesize; |
50 | int iway; |
51 | int dcache_shift; |
52 | int dlinesize; |
53 | int dway; |
54 | int l2cache_shift; |
55 | int l2linesize; |
56 | int l2way; |
57 | int altivec; |
58 | |
59 | /* TODO: POWER vs PowerPC? */ |
60 | }; |
61 | |
62 | /* Flags: */ |
63 | #define PPC_NOFP 1 |
64 | #define PPC_601 2 |
65 | #define PPC_603 4 |
66 | #define PPC_NO_DEC 8 /* No DEC (decrementer) SPR */ |
67 | |
68 | /* |
69 | * TODO: Most of these just bogus |
70 | */ |
71 | |
72 | #define PPC_CPU_TYPE_DEFS { \ |
73 | { "PPC405GP", 0x40110000, 32, PPC_NOFP|PPC_NO_DEC, \ |
74 | 13,5,2, 13,5,2, 0,5,1, 0 }, \ |
75 | { "PPC601", 0, 32, PPC_601, 14,5,4, 14,5,4, 0,0,0, 0 },\ |
76 | { "PPC603", 0x00030302, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 },\ |
77 | { "PPC603e", 0x00060104, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 },\ |
78 | { "PPC604", 0x00040304, 32, 0, 15,5,4, 15,5,4, 0,0,0, 0 }, \ |
79 | { "PPC620", 0x00140000, 64, 0, 15,5,4, 15,5,4, 0,0,0, 0 }, \ |
80 | { "MPC7400", 0x000c0000, 32, 0, 15,5,2, 15,5,2, 19,5,1, 1 }, \ |
81 | { "PPC750", 0x00084202, 32, 0, 15,5,2, 15,5,2, 20,5,1, 0 }, \ |
82 | { "G4e", 0, 32, 0, 15,5,8, 15,5,8, 18,5,8, 1 }, \ |
83 | { "PPC970", 0x00390000, 64, 0, 16,7,1, 15,7,2, 19,7,1, 1 }, \ |
84 | { NULL, 0, 0,0,0,0,0,0,0,0,0,0,0,0 } \ |
85 | } |
86 | |
87 | #define PPC_NGPRS 32 |
88 | #define PPC_NFPRS 32 |
89 | #define PPC_NVRS 32 |
90 | #define PPC_N_TGPRS 4 |
91 | |
92 | #define PPC_N_IC_ARGS 3 |
93 | #define PPC_INSTR_ALIGNMENT_SHIFT 2 |
94 | #define PPC_IC_ENTRIES_SHIFT 10 |
95 | #define PPC_IC_ENTRIES_PER_PAGE (1 << PPC_IC_ENTRIES_SHIFT) |
96 | #define PPC_PC_TO_IC_ENTRY(a) (((a)>>PPC_INSTR_ALIGNMENT_SHIFT) \ |
97 | & (PPC_IC_ENTRIES_PER_PAGE-1)) |
98 | #define PPC_ADDR_TO_PAGENR(a) ((a) >> (PPC_IC_ENTRIES_SHIFT \ |
99 | + PPC_INSTR_ALIGNMENT_SHIFT)) |
100 | |
101 | #define PPC_L2N 17 |
102 | #define PPC_L3N 18 |
103 | |
104 | DYNTRANS_MISC_DECLARATIONS(ppc,PPC,uint64_t) |
105 | DYNTRANS_MISC64_DECLARATIONS(ppc,PPC,uint8_t) |
106 | |
107 | #define PPC_MAX_VPH_TLB_ENTRIES 128 |
108 | |
109 | |
110 | struct ppc_cpu { |
111 | struct ppc_cpu_type_def cpu_type; |
112 | |
113 | uint64_t of_emul_addr; |
114 | |
115 | int mode; /* MODE_PPC or MODE_POWER */ |
116 | int bits; /* 32 or 64 */ |
117 | |
118 | int irq_asserted; /* External Interrupt flag */ |
119 | int dec_intr_pending;/* Decrementer interrupt pending */ |
120 | uint64_t zero; /* A zero register */ |
121 | |
122 | uint32_t cr; /* Condition Register */ |
123 | uint32_t fpscr; /* FP Status and Control Register */ |
124 | uint64_t gpr[PPC_NGPRS]; /* General Purpose Registers */ |
125 | uint64_t fpr[PPC_NFPRS]; /* Floating-Point Registers */ |
126 | |
127 | uint64_t vr_hi[PPC_NVRS];/* 128-bit Vector registers */ |
128 | uint64_t vr_lo[PPC_NVRS];/* (Hi and lo 64-bit parts) */ |
129 | |
130 | uint64_t msr; /* Machine state register */ |
131 | uint64_t tgpr[PPC_N_TGPRS];/*Temporary gpr 0..3 */ |
132 | |
133 | uint32_t sr[16]; /* Segment registers. */ |
134 | uint64_t spr[1024]; |
135 | |
136 | uint64_t ll_addr; /* Load-linked / store-conditional */ |
137 | int ll_bit; |
138 | |
139 | |
140 | /* |
141 | * Instruction translation cache and Virtual->Physical->Host |
142 | * address translation: |
143 | */ |
144 | DYNTRANS_ITC(ppc) |
145 | VPH_TLBS(ppc,PPC) |
146 | VPH32(ppc,PPC,uint64_t,uint8_t) |
147 | VPH64(ppc,PPC,uint8_t) |
148 | }; |
149 | |
150 | |
151 | /* Machine status word bits: (according to Book 3) */ |
152 | #define PPC_MSR_SF (1ULL << 63) /* Sixty-Four-Bit Mode */ |
153 | /* bits 62..61 are reserved */ |
154 | #define PPC_MSR_HV (1ULL << 60) /* Hypervisor */ |
155 | /* bits 59..17 are reserved */ |
156 | #define PPC_MSR_VEC (1 << 25) /* Altivec Enable */ |
157 | #define PPC_MSR_TGPR (1 << 17) /* Temporary gpr0..3 */ |
158 | #define PPC_MSR_ILE (1 << 16) /* Interrupt Little-Endian Mode */ |
159 | #define PPC_MSR_EE (1 << 15) /* External Interrupt Enable */ |
160 | #define PPC_MSR_PR (1 << 14) /* Problem/Privilege State */ |
161 | #define PPC_MSR_FP (1 << 13) /* Floating-Point Available */ |
162 | #define PPC_MSR_ME (1 << 12) /* Machine Check Interrupt Enable */ |
163 | #define PPC_MSR_FE0 (1 << 11) /* Floating-Point Exception Mode 0 */ |
164 | #define PPC_MSR_SE (1 << 10) /* Single-Step Trace Enable */ |
165 | #define PPC_MSR_BE (1 << 9) /* Branch Trace Enable */ |
166 | #define PPC_MSR_FE1 (1 << 8) /* Floating-Point Exception Mode 1 */ |
167 | #define PPC_MSR_IP (1 << 6) /* Vector Table at 0xfff00000 */ |
168 | #define PPC_MSR_IR (1 << 5) /* Instruction Relocate */ |
169 | #define PPC_MSR_DR (1 << 4) /* Data Relocate */ |
170 | #define PPC_MSR_PMM (1 << 2) /* Performance Monitor Mark */ |
171 | #define PPC_MSR_RI (1 << 1) /* Recoverable Interrupt */ |
172 | #define PPC_MSR_LE (1) /* Little-Endian Mode */ |
173 | |
174 | /* Floating-point Status: */ |
175 | #define PPC_FPSCR_FX (1 << 31) /* Exception summary */ |
176 | #define PPC_FPSCR_FEX (1 << 30) /* Enabled Exception summary */ |
177 | #define PPC_FPSCR_VX (1 << 29) /* Invalid Operation summary */ |
178 | /* .. TODO */ |
179 | #define PPC_FPSCR_VXNAN (1 << 24) |
180 | /* .. TODO */ |
181 | #define PPC_FPSCR_FPCC 0x0000f000 |
182 | #define PPC_FPSCR_FPCC_SHIFT 12 |
183 | #define PPC_FPSCR_FL (1 << 15) /* Less than */ |
184 | #define PPC_FPSCR_FG (1 << 14) /* Greater than */ |
185 | #define PPC_FPSCR_FE (1 << 13) /* Equal or Zero */ |
186 | #define PPC_FPSCR_FU (1 << 12) /* Unordered or NaN */ |
187 | |
188 | /* Exceptions: */ |
189 | #define PPC_EXCEPTION_DSI 0x3 /* Data Storage Interrupt */ |
190 | #define PPC_EXCEPTION_ISI 0x4 /* Instruction Storage Interrupt */ |
191 | #define PPC_EXCEPTION_EI 0x5 /* External interrupt */ |
192 | #define PPC_EXCEPTION_FPU 0x8 /* Floating-Point unavailable */ |
193 | #define PPC_EXCEPTION_DEC 0x9 /* Decrementer */ |
194 | #define PPC_EXCEPTION_SC 0xc /* Syscall */ |
195 | |
196 | /* XER bits: */ |
197 | #define PPC_XER_SO (1UL << 31) /* Summary Overflow */ |
198 | #define PPC_XER_OV (1 << 30) /* Overflow */ |
199 | #define PPC_XER_CA (1 << 29) /* Carry */ |
200 | |
201 | |
202 | /* cpu_ppc.c: */ |
203 | int ppc_run_instr(struct cpu *cpu); |
204 | int ppc32_run_instr(struct cpu *cpu); |
205 | void ppc_exception(struct cpu *cpu, int exception_nr); |
206 | void ppc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
207 | unsigned char *host_page, int writeflag, uint64_t paddr_page); |
208 | void ppc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
209 | unsigned char *host_page, int writeflag, uint64_t paddr_page); |
210 | void ppc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
211 | void ppc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
212 | void ppc_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
213 | void ppc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
214 | void ppc_init_64bit_dummy_tables(struct cpu *cpu); |
215 | int ppc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
216 | unsigned char *data, size_t len, int writeflag, int cache_flags); |
217 | int ppc_cpu_family_init(struct cpu_family *); |
218 | |
219 | /* memory_ppc.c: */ |
220 | int ppc_translate_v2p(struct cpu *cpu, uint64_t vaddr, |
221 | uint64_t *return_addr, int flags); |
222 | |
223 | #endif /* CPU_PPC_H */ |
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