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* SUCH DAMAGE. |
* SUCH DAMAGE. |
29 |
* |
* |
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* |
* |
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* $Id: cpu_ppc.h,v 1.29 2005/08/14 23:44:23 debug Exp $ |
* $Id: cpu_ppc.h,v 1.38 2005/09/24 23:44:19 debug Exp $ |
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*/ |
*/ |
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|
|
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#include "misc.h" |
#include "misc.h" |
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/* PPC CPU types: */ |
/* PPC CPU types: */ |
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struct ppc_cpu_type_def { |
struct ppc_cpu_type_def { |
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char *name; |
char *name; |
45 |
|
int pvr; |
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int bits; |
int bits; |
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int flags; |
int flags; |
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int icache_shift; |
int icache_shift; |
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|
int ilinesize; |
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int iway; |
int iway; |
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int dcache_shift; |
int dcache_shift; |
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|
int dlinesize; |
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int dway; |
int dway; |
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int l2cache_shift; |
int l2cache_shift; |
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|
int l2linesize; |
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int l2way; |
int l2way; |
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int altivec; |
int altivec; |
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|
|
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#define PPC_NOFP 1 |
#define PPC_NOFP 1 |
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/* TODO: Most of these just bogus */ |
/* TODO: Most of these just bogus */ |
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|
|
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#define PPC_CPU_TYPE_DEFS { \ |
#define PPC_CPU_TYPE_DEFS { \ |
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{ "PPC405GP", 32, PPC_NOFP, 15, 2, 15, 2, 20, 1, 0 }, \ |
{ "PPC405GP", 0, 32, PPC_NOFP, 15,5,2, 15,5,2, 20,5,1, 0 }, \ |
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{ "PPC603e", 32, 0, 14, 4, 14, 4, 0, 0, 0 }, \ |
{ "PPC603e", 0, 32, 0, 14,5,4, 14,5,4, 0,0,0, 0 }, \ |
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{ "MPC7400", 32, 0, 15, 2, 15, 2, 19, 1, 1 }, \ |
{ "MPC7400", 0x000c0000, 32, 0, 15,5,2, 15,5,2, 19,5,1, 1 }, \ |
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{ "PPC750", 32, 0, 15, 2, 15, 2, 20, 1, 0 }, \ |
{ "PPC750", 0x00084202, 32, 0, 15,5,2, 15,5,2, 20,5,1, 0 }, \ |
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{ "G4e", 32, 0, 15, 8, 15, 8, 18, 8, 1 }, \ |
{ "G4e", 0, 32, 0, 15,5,8, 15,5,8, 18,5,8, 1 }, \ |
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{ "PPC970", 64, 0, 16, 1, 15, 2, 19, 1, 1 }, \ |
{ "PPC970", 0x00390000, 64, 0, 16,7,1, 15,7,2, 19,7,1, 1 }, \ |
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{ NULL, 0, 0, 0,0, 0,0, 0,0, 0 } \ |
{ NULL, 0, 0,0,0,0,0,0,0,0,0,0,0,0 } \ |
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}; |
} |
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|
|
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#define PPC_NGPRS 32 |
#define PPC_NGPRS 32 |
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#define PPC_NFPRS 32 |
#define PPC_NFPRS 32 |
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struct ppc_cpu_type_def cpu_type; |
struct ppc_cpu_type_def cpu_type; |
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|
|
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uint64_t of_emul_addr; |
uint64_t of_emul_addr; |
|
uint64_t pc_last; |
|
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|
|
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int mode; /* MODE_PPC or MODE_POWER */ |
int mode; /* MODE_PPC or MODE_POWER */ |
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int bits; /* 32 or 64 */ |
int bits; /* 32 or 64 */ |
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uint32_t tbu; /* Time Base Upper */ |
uint32_t tbu; /* Time Base Upper */ |
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uint32_t dec; /* Decrementer */ |
uint32_t dec; /* Decrementer */ |
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uint32_t hdec; /* Hypervisor Decrementer */ |
uint32_t hdec; /* Hypervisor Decrementer */ |
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|
uint64_t sdr1; /* Storage Descriptor Register */ |
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uint64_t srr0; /* Supervisor save/restore 0 */ |
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|
uint64_t srr1; /* Supervisor save/restore 1 */ |
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uint64_t ssr0; /* Machine status save/restore |
uint64_t ssr0; /* Machine status save/restore |
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register 0 */ |
register 0 */ |
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uint64_t ssr1; /* Machine status save/restore |
uint64_t ssr1; /* Machine status save/restore |
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uint64_t sprg1; /* Special Purpose Register G1 */ |
uint64_t sprg1; /* Special Purpose Register G1 */ |
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uint64_t sprg2; /* Special Purpose Register G2 */ |
uint64_t sprg2; /* Special Purpose Register G2 */ |
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uint64_t sprg3; /* Special Purpose Register G3 */ |
uint64_t sprg3; /* Special Purpose Register G3 */ |
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|
uint64_t dbsr; /* Debug Status Register */ |
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uint32_t pvr; /* Processor Version Register */ |
uint32_t pvr; /* Processor Version Register */ |
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uint32_t pir; /* Processor ID */ |
uint32_t pir; /* Processor ID */ |
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|
|
152 |
|
/* TODO: 64-bit SRs? (Segment registers) */ |
153 |
|
uint32_t sr[16]; |
154 |
|
|
155 |
|
/* TODO: 64-bit BATs? */ |
156 |
|
uint32_t ibat_u[4]; |
157 |
|
uint32_t ibat_l[4]; |
158 |
|
uint32_t dbat_u[4]; |
159 |
|
uint32_t dbat_l[4]; |
160 |
|
|
161 |
|
uint64_t ll_addr; /* Load-linked / store-conditional */ |
162 |
|
int ll_bit; |
163 |
|
|
164 |
|
|
165 |
/* |
/* |
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* Instruction translation cache: |
* Instruction translation cache: |
219 |
/* cpu_ppc.c: */ |
/* cpu_ppc.c: */ |
220 |
void ppc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
void ppc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void ppc_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t paddr); |
void ppc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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void ppc_invalidate_code_translation_caches(struct cpu *cpu); |
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
224 |
|
void ppc_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int); |
225 |
|
void ppc32_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int); |
226 |
|
void ppc_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
227 |
|
void ppc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
228 |
int ppc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
int ppc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
229 |
unsigned char *data, size_t len, int writeflag, int cache_flags); |
unsigned char *data, size_t len, int writeflag, int cache_flags); |
230 |
int ppc_cpu_family_init(struct cpu_family *); |
int ppc_cpu_family_init(struct cpu_family *); |
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|
|
232 |
|
/* memory_ppc.c: */ |
233 |
|
int ppc_translate_address(struct cpu *cpu, uint64_t vaddr, |
234 |
|
uint64_t *return_addr, int flags); |
235 |
|
|
236 |
#endif /* CPU_PPC_H */ |
#endif /* CPU_PPC_H */ |