--- trunk/src/include/cpu_ppc.h 2007/10/08 16:19:16 19 +++ trunk/src/include/cpu_ppc.h 2007/10/08 16:19:23 20 @@ -28,7 +28,7 @@ * SUCH DAMAGE. * * - * $Id: cpu_ppc.h,v 1.41 2005/10/27 14:01:15 debug Exp $ + * $Id: cpu_ppc.h,v 1.55 2005/11/24 01:15:07 debug Exp $ */ #include "misc.h" @@ -61,11 +61,17 @@ /* Flags: */ #define PPC_NOFP 1 +#define PPC_601 2 +#define PPC_603 4 /* TODO: Most of these just bogus */ #define PPC_CPU_TYPE_DEFS { \ { "PPC405GP", 0, 32, PPC_NOFP, 15,5,2, 15,5,2, 20,5,1, 0 }, \ - { "PPC603e", 0, 32, 0, 14,5,4, 14,5,4, 0,0,0, 0 }, \ + { "PPC601", 0, 32, PPC_601, 14,5,4, 14,5,4, 0,0,0, 0 }, \ + { "PPC603", 0x00030302, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 }, \ + { "PPC603e", 0x00060104, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 }, \ + { "PPC604", 0x00040304, 32, 0, 15,5,4, 15,5,4, 0,0,0, 0 }, \ + { "PPC620", 0x00140000, 64, 0, 15,5,4, 15,5,4, 0,0,0, 0 }, \ { "MPC7400", 0x000c0000, 32, 0, 15,5,2, 15,5,2, 19,5,1, 1 }, \ { "PPC750", 0x00084202, 32, 0, 15,5,2, 15,5,2, 20,5,1, 0 }, \ { "G4e", 0, 32, 0, 15,5,8, 15,5,8, 18,5,8, 1 }, \ @@ -75,7 +81,7 @@ #define PPC_NGPRS 32 #define PPC_NFPRS 32 - +#define PPC_N_TGPRS 4 #define PPC_N_IC_ARGS 3 #define PPC_INSTR_ALIGNMENT_SHIFT 2 @@ -101,14 +107,14 @@ #define PPC_N_VPH_ENTRIES 1048576 -#define PPC_MAX_VPH_TLB_ENTRIES 256 +#define PPC_MAX_VPH_TLB_ENTRIES 128 struct ppc_vpg_tlb_entry { - int valid; - int writeflag; + uint8_t valid; + uint8_t writeflag; int64_t timestamp; - unsigned char *host_page; uint64_t vaddr_page; uint64_t paddr_page; + unsigned char *host_page; }; struct ppc_cpu { @@ -119,44 +125,20 @@ int mode; /* MODE_PPC or MODE_POWER */ int bits; /* 32 or 64 */ + int irq_asserted; /* External Interrupt flag */ + int dec_intr_pending;/* Decrementer interrupt pending */ uint64_t zero; /* A zero register */ uint32_t cr; /* Condition Register */ uint32_t fpscr; /* FP Status and Control Register */ - uint64_t lr; /* Link Register */ - uint64_t ctr; /* Count Register */ uint64_t gpr[PPC_NGPRS]; /* General Purpose Registers */ - uint64_t xer; /* FP Exception Register */ uint64_t fpr[PPC_NFPRS]; /* Floating-Point Registers */ - uint32_t tbl; /* Time Base Lower */ - uint32_t tbu; /* Time Base Upper */ - uint32_t dec; /* Decrementer */ - uint32_t hdec; /* Hypervisor Decrementer */ - uint64_t sdr1; /* Storage Descriptor Register */ - uint64_t srr0; /* Supervisor save/restore 0 */ - uint64_t srr1; /* Supervisor save/restore 1 */ - uint64_t ssr0; /* Machine status save/restore - register 0 */ - uint64_t ssr1; /* Machine status save/restore - register 1 */ uint64_t msr; /* Machine state register */ - uint64_t sprg0; /* Special Purpose Register G0 */ - uint64_t sprg1; /* Special Purpose Register G1 */ - uint64_t sprg2; /* Special Purpose Register G2 */ - uint64_t sprg3; /* Special Purpose Register G3 */ - uint64_t dbsr; /* Debug Status Register */ - uint32_t pvr; /* Processor Version Register */ - uint32_t pir; /* Processor ID */ - - /* TODO: 64-bit SRs? (Segment registers) */ - uint32_t sr[16]; - - /* TODO: 64-bit BATs? */ - uint32_t ibat_u[4]; - uint32_t ibat_l[4]; - uint32_t dbat_u[4]; - uint32_t dbat_l[4]; + uint64_t tgpr[PPC_N_TGPRS];/*Temporary gpr 0..3 */ + + uint32_t sr[16]; /* Segment registers. */ + uint64_t spr[1024]; uint64_t ll_addr; /* Load-linked / store-conditional */ int ll_bit; @@ -173,6 +155,8 @@ struct ppc_instr_call *cur_ic_page; struct ppc_instr_call *next_ic; + void (*combination_check)(struct cpu *, + struct ppc_instr_call *, int low_addr); /* * Virtual -> physical -> host address translation: @@ -189,7 +173,7 @@ struct ppc_tc_physpage *phys_page[PPC_N_VPH_ENTRIES]; uint32_t phystranslation[PPC_N_VPH_ENTRIES/32]; - int16_t vaddr_to_tlbindex[PPC_N_VPH_ENTRIES]; + uint8_t vaddr_to_tlbindex[PPC_N_VPH_ENTRIES]; }; @@ -198,21 +182,46 @@ /* bits 62..61 are reserved */ #define PPC_MSR_HV (1ULL << 60) /* Hypervisor */ /* bits 59..17 are reserved */ +#define PPC_MSR_VEC (1 << 25) /* Altivec Enable */ +#define PPC_MSR_TGPR (1 << 17) /* Temporary gpr0..3 */ #define PPC_MSR_ILE (1 << 16) /* Interrupt Little-Endian Mode */ #define PPC_MSR_EE (1 << 15) /* External Interrupt Enable */ -#define PPC_MSR_PR (1 << 14) /* Problem State */ +#define PPC_MSR_PR (1 << 14) /* Problem/Privilege State */ #define PPC_MSR_FP (1 << 13) /* Floating-Point Available */ #define PPC_MSR_ME (1 << 12) /* Machine Check Interrupt Enable */ #define PPC_MSR_FE0 (1 << 11) /* Floating-Point Exception Mode 0 */ #define PPC_MSR_SE (1 << 10) /* Single-Step Trace Enable */ #define PPC_MSR_BE (1 << 9) /* Branch Trace Enable */ #define PPC_MSR_FE1 (1 << 8) /* Floating-Point Exception Mode 1 */ +#define PPC_MSR_IP (1 << 6) /* Vector Table at 0xfff00000 */ #define PPC_MSR_IR (1 << 5) /* Instruction Relocate */ #define PPC_MSR_DR (1 << 4) /* Data Relocate */ #define PPC_MSR_PMM (1 << 2) /* Performance Monitor Mark */ #define PPC_MSR_RI (1 << 1) /* Recoverable Interrupt */ #define PPC_MSR_LE (1) /* Little-Endian Mode */ +/* Floating-point Status: */ +#define PPC_FPSCR_FX (1 << 31) /* Exception summary */ +#define PPC_FPSCR_FEX (1 << 30) /* Enabled Exception summary */ +#define PPC_FPSCR_VX (1 << 29) /* Invalid Operation summary */ +/* .. TODO */ +#define PPC_FPSCR_VXNAN (1 << 24) +/* .. TODO */ +#define PPC_FPSCR_FPCC 0x0000f000 +#define PPC_FPSCR_FPCC_SHIFT 12 +#define PPC_FPSCR_FL (1 << 15) /* Less than */ +#define PPC_FPSCR_FG (1 << 14) /* Greater than */ +#define PPC_FPSCR_FE (1 << 13) /* Equal or Zero */ +#define PPC_FPSCR_FU (1 << 12) /* Unordered or NaN */ + +/* Exceptions: */ +#define PPC_EXCEPTION_DSI 0x3 /* Data Storage Interrupt */ +#define PPC_EXCEPTION_ISI 0x4 /* Instruction Storage Interrupt */ +#define PPC_EXCEPTION_EI 0x5 /* External interrupt */ +#define PPC_EXCEPTION_FPU 0x8 /* Floating-Point unavailable */ +#define PPC_EXCEPTION_DEC 0x9 /* Decrementer */ +#define PPC_EXCEPTION_SC 0xc /* Syscall */ + /* XER bits: */ #define PPC_XER_SO (1UL << 31) /* Summary Overflow */ #define PPC_XER_OV (1 << 30) /* Overflow */ @@ -220,6 +229,7 @@ /* cpu_ppc.c: */ +void ppc_exception(struct cpu *cpu, int exception_nr); void ppc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page); void ppc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,