/[gxemul]/trunk/src/include/cpu_ppc.h
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Annotation of /trunk/src/include/cpu_ppc.h

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Revision 22 - (hide annotations)
Mon Oct 8 16:19:37 2007 UTC (16 years, 6 months ago) by dpavlin
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File size: 7752 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============
1 dpavlin 4 #ifndef CPU_PPC_H
2     #define CPU_PPC_H
3    
4     /*
5 dpavlin 22 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
6 dpavlin 4 *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31 dpavlin 22 * $Id: cpu_ppc.h,v 1.60 2006/02/09 22:40:27 debug Exp $
32 dpavlin 4 */
33    
34     #include "misc.h"
35    
36    
37     struct cpu_family;
38    
39     #define MODE_PPC 0
40     #define MODE_POWER 1
41    
42     /* PPC CPU types: */
43     struct ppc_cpu_type_def {
44     char *name;
45 dpavlin 14 int pvr;
46 dpavlin 4 int bits;
47     int flags;
48     int icache_shift;
49 dpavlin 14 int ilinesize;
50 dpavlin 4 int iway;
51     int dcache_shift;
52 dpavlin 14 int dlinesize;
53 dpavlin 4 int dway;
54     int l2cache_shift;
55 dpavlin 14 int l2linesize;
56 dpavlin 4 int l2way;
57     int altivec;
58    
59     /* TODO: POWER vs PowerPC? */
60     };
61    
62     /* Flags: */
63     #define PPC_NOFP 1
64 dpavlin 20 #define PPC_601 2
65     #define PPC_603 4
66 dpavlin 22 #define PPC_NO_DEC 8 /* No DEC (decrementer) SPR */
67    
68 dpavlin 4 /* TODO: Most of these just bogus */
69    
70 dpavlin 14 #define PPC_CPU_TYPE_DEFS { \
71 dpavlin 22 { "PPC405GP", 0x40110000, 32, PPC_NOFP|PPC_NO_DEC, \
72     13,5,2, 13,5,2, 0,5,1, 0 }, \
73     { "PPC601", 0, 32, PPC_601, 14,5,4, 14,5,4, 0,0,0, 0 },\
74     { "PPC603", 0x00030302, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 },\
75     { "PPC603e", 0x00060104, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 },\
76 dpavlin 20 { "PPC604", 0x00040304, 32, 0, 15,5,4, 15,5,4, 0,0,0, 0 }, \
77     { "PPC620", 0x00140000, 64, 0, 15,5,4, 15,5,4, 0,0,0, 0 }, \
78 dpavlin 14 { "MPC7400", 0x000c0000, 32, 0, 15,5,2, 15,5,2, 19,5,1, 1 }, \
79     { "PPC750", 0x00084202, 32, 0, 15,5,2, 15,5,2, 20,5,1, 0 }, \
80     { "G4e", 0, 32, 0, 15,5,8, 15,5,8, 18,5,8, 1 }, \
81     { "PPC970", 0x00390000, 64, 0, 16,7,1, 15,7,2, 19,7,1, 1 }, \
82     { NULL, 0, 0,0,0,0,0,0,0,0,0,0,0,0 } \
83     }
84 dpavlin 4
85     #define PPC_NGPRS 32
86     #define PPC_NFPRS 32
87 dpavlin 20 #define PPC_N_TGPRS 4
88 dpavlin 4
89 dpavlin 12 #define PPC_N_IC_ARGS 3
90     #define PPC_INSTR_ALIGNMENT_SHIFT 2
91     #define PPC_IC_ENTRIES_SHIFT 10
92     #define PPC_IC_ENTRIES_PER_PAGE (1 << PPC_IC_ENTRIES_SHIFT)
93     #define PPC_PC_TO_IC_ENTRY(a) (((a)>>PPC_INSTR_ALIGNMENT_SHIFT) \
94     & (PPC_IC_ENTRIES_PER_PAGE-1))
95     #define PPC_ADDR_TO_PAGENR(a) ((a) >> (PPC_IC_ENTRIES_SHIFT \
96     + PPC_INSTR_ALIGNMENT_SHIFT))
97    
98 dpavlin 22 DYNTRANS_MISC_DECLARATIONS(ppc,PPC,uint64_t)
99 dpavlin 12
100 dpavlin 22 #define PPC_MAX_VPH_TLB_ENTRIES 128
101 dpavlin 12
102    
103 dpavlin 4 struct ppc_cpu {
104     struct ppc_cpu_type_def cpu_type;
105    
106     uint64_t of_emul_addr;
107    
108     int mode; /* MODE_PPC or MODE_POWER */
109     int bits; /* 32 or 64 */
110    
111 dpavlin 20 int irq_asserted; /* External Interrupt flag */
112     int dec_intr_pending;/* Decrementer interrupt pending */
113 dpavlin 12 uint64_t zero; /* A zero register */
114    
115 dpavlin 4 uint32_t cr; /* Condition Register */
116     uint32_t fpscr; /* FP Status and Control Register */
117     uint64_t gpr[PPC_NGPRS]; /* General Purpose Registers */
118     uint64_t fpr[PPC_NFPRS]; /* Floating-Point Registers */
119    
120     uint64_t msr; /* Machine state register */
121 dpavlin 20 uint64_t tgpr[PPC_N_TGPRS];/*Temporary gpr 0..3 */
122 dpavlin 12
123 dpavlin 20 uint32_t sr[16]; /* Segment registers. */
124     uint64_t spr[1024];
125 dpavlin 12
126 dpavlin 14 uint64_t ll_addr; /* Load-linked / store-conditional */
127     int ll_bit;
128    
129    
130 dpavlin 12 /*
131 dpavlin 22 * Instruction translation cache and Virtual->Physical->Host
132     * address translation:
133 dpavlin 12 */
134 dpavlin 22 DYNTRANS_ITC(ppc)
135     VPH_TLBS(ppc,PPC)
136     VPH32(ppc,PPC,uint64_t,uint8_t)
137     VPH64(ppc,PPC,uint8_t)
138 dpavlin 4 };
139    
140    
141     /* Machine status word bits: (according to Book 3) */
142     #define PPC_MSR_SF (1ULL << 63) /* Sixty-Four-Bit Mode */
143     /* bits 62..61 are reserved */
144     #define PPC_MSR_HV (1ULL << 60) /* Hypervisor */
145     /* bits 59..17 are reserved */
146 dpavlin 20 #define PPC_MSR_VEC (1 << 25) /* Altivec Enable */
147     #define PPC_MSR_TGPR (1 << 17) /* Temporary gpr0..3 */
148 dpavlin 4 #define PPC_MSR_ILE (1 << 16) /* Interrupt Little-Endian Mode */
149     #define PPC_MSR_EE (1 << 15) /* External Interrupt Enable */
150 dpavlin 20 #define PPC_MSR_PR (1 << 14) /* Problem/Privilege State */
151 dpavlin 4 #define PPC_MSR_FP (1 << 13) /* Floating-Point Available */
152     #define PPC_MSR_ME (1 << 12) /* Machine Check Interrupt Enable */
153     #define PPC_MSR_FE0 (1 << 11) /* Floating-Point Exception Mode 0 */
154     #define PPC_MSR_SE (1 << 10) /* Single-Step Trace Enable */
155     #define PPC_MSR_BE (1 << 9) /* Branch Trace Enable */
156     #define PPC_MSR_FE1 (1 << 8) /* Floating-Point Exception Mode 1 */
157 dpavlin 20 #define PPC_MSR_IP (1 << 6) /* Vector Table at 0xfff00000 */
158 dpavlin 4 #define PPC_MSR_IR (1 << 5) /* Instruction Relocate */
159     #define PPC_MSR_DR (1 << 4) /* Data Relocate */
160     #define PPC_MSR_PMM (1 << 2) /* Performance Monitor Mark */
161     #define PPC_MSR_RI (1 << 1) /* Recoverable Interrupt */
162     #define PPC_MSR_LE (1) /* Little-Endian Mode */
163    
164 dpavlin 20 /* Floating-point Status: */
165     #define PPC_FPSCR_FX (1 << 31) /* Exception summary */
166     #define PPC_FPSCR_FEX (1 << 30) /* Enabled Exception summary */
167     #define PPC_FPSCR_VX (1 << 29) /* Invalid Operation summary */
168     /* .. TODO */
169     #define PPC_FPSCR_VXNAN (1 << 24)
170     /* .. TODO */
171     #define PPC_FPSCR_FPCC 0x0000f000
172     #define PPC_FPSCR_FPCC_SHIFT 12
173     #define PPC_FPSCR_FL (1 << 15) /* Less than */
174     #define PPC_FPSCR_FG (1 << 14) /* Greater than */
175     #define PPC_FPSCR_FE (1 << 13) /* Equal or Zero */
176     #define PPC_FPSCR_FU (1 << 12) /* Unordered or NaN */
177    
178     /* Exceptions: */
179     #define PPC_EXCEPTION_DSI 0x3 /* Data Storage Interrupt */
180     #define PPC_EXCEPTION_ISI 0x4 /* Instruction Storage Interrupt */
181     #define PPC_EXCEPTION_EI 0x5 /* External interrupt */
182     #define PPC_EXCEPTION_FPU 0x8 /* Floating-Point unavailable */
183     #define PPC_EXCEPTION_DEC 0x9 /* Decrementer */
184     #define PPC_EXCEPTION_SC 0xc /* Syscall */
185    
186 dpavlin 4 /* XER bits: */
187 dpavlin 18 #define PPC_XER_SO (1UL << 31) /* Summary Overflow */
188 dpavlin 4 #define PPC_XER_OV (1 << 30) /* Overflow */
189     #define PPC_XER_CA (1 << 29) /* Carry */
190    
191    
192     /* cpu_ppc.c: */
193 dpavlin 20 void ppc_exception(struct cpu *cpu, int exception_nr);
194 dpavlin 12 void ppc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
195     unsigned char *host_page, int writeflag, uint64_t paddr_page);
196 dpavlin 14 void ppc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
197     unsigned char *host_page, int writeflag, uint64_t paddr_page);
198 dpavlin 18 void ppc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
199     void ppc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
200 dpavlin 14 void ppc_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
201     void ppc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
202 dpavlin 4 int ppc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
203     unsigned char *data, size_t len, int writeflag, int cache_flags);
204     int ppc_cpu_family_init(struct cpu_family *);
205    
206 dpavlin 14 /* memory_ppc.c: */
207     int ppc_translate_address(struct cpu *cpu, uint64_t vaddr,
208     uint64_t *return_addr, int flags);
209 dpavlin 4
210     #endif /* CPU_PPC_H */
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