src/include/cpu_ppc.h

#ifndef CPU_PPC_H
#define CPU_PPC_H

/*
 *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_ppc.h,v 1.41 2005/10/27 14:01:15 debug Exp $
 */

#include "misc.h"


struct cpu_family;

#define MODE_PPC                0
#define MODE_POWER              1

/*  PPC CPU types:  */
struct ppc_cpu_type_def { 
        char            *name;
        int             pvr;
        int             bits;
        int             flags;
        int             icache_shift;
        int             ilinesize;
        int             iway;
        int             dcache_shift;
        int             dlinesize;
        int             dway;
        int             l2cache_shift;
        int             l2linesize;
        int             l2way;
        int             altivec;

        /*  TODO: POWER vs PowerPC?  */
};

/*  Flags:  */
#define PPC_NOFP                1
/*  TODO: Most of these just bogus  */

#define PPC_CPU_TYPE_DEFS       {                                       \
        { "PPC405GP",   0,          32, PPC_NOFP, 15,5,2, 15,5,2, 20,5,1, 0 }, \
        { "PPC603e",    0,          32, 0, 14,5,4, 14,5,4, 0,0,0, 0 },  \
        { "MPC7400",    0x000c0000, 32, 0, 15,5,2, 15,5,2, 19,5,1, 1 }, \
        { "PPC750",     0x00084202, 32, 0, 15,5,2, 15,5,2, 20,5,1, 0 }, \
        { "G4e",        0,          32, 0, 15,5,8, 15,5,8, 18,5,8, 1 }, \
        { "PPC970",     0x00390000, 64, 0, 16,7,1, 15,7,2, 19,7,1, 1 }, \
        { NULL,         0,          0,0,0,0,0,0,0,0,0,0,0,0 }           \
        }

#define PPC_NGPRS               32
#define PPC_NFPRS               32


#define PPC_N_IC_ARGS                   3
#define PPC_INSTR_ALIGNMENT_SHIFT       2
#define PPC_IC_ENTRIES_SHIFT            10
#define PPC_IC_ENTRIES_PER_PAGE         (1 << PPC_IC_ENTRIES_SHIFT)
#define PPC_PC_TO_IC_ENTRY(a)           (((a)>>PPC_INSTR_ALIGNMENT_SHIFT) \
                                        & (PPC_IC_ENTRIES_PER_PAGE-1))
#define PPC_ADDR_TO_PAGENR(a)           ((a) >> (PPC_IC_ENTRIES_SHIFT \
                                        + PPC_INSTR_ALIGNMENT_SHIFT))

struct ppc_instr_call {
        void    (*f)(struct cpu *, struct ppc_instr_call *);
        size_t  arg[PPC_N_IC_ARGS];
};

/*  Translation cache struct for each physical page:  */
struct ppc_tc_physpage {
        struct ppc_instr_call ics[PPC_IC_ENTRIES_PER_PAGE + 1];
        uint32_t        next_ofs;       /*  or 0 for end of chain  */
        int             flags;
        uint64_t        physaddr;
};

#define PPC_N_VPH_ENTRIES               1048576

#define PPC_MAX_VPH_TLB_ENTRIES         256
struct ppc_vpg_tlb_entry {
        int             valid;
        int             writeflag;
        int64_t         timestamp;
        unsigned char   *host_page;
        uint64_t        vaddr_page;
        uint64_t        paddr_page;
};

struct ppc_cpu {
        struct ppc_cpu_type_def cpu_type;

        uint64_t        of_emul_addr;

        int             mode;           /*  MODE_PPC or MODE_POWER  */
        int             bits;           /*  32 or 64  */

        uint64_t        zero;           /*  A zero register  */

        uint32_t        cr;             /*  Condition Register  */
        uint32_t        fpscr;          /*  FP Status and Control Register  */
        uint64_t        lr;             /*  Link Register  */
        uint64_t        ctr;            /*  Count Register  */
        uint64_t        gpr[PPC_NGPRS]; /*  General Purpose Registers  */
        uint64_t        xer;            /*  FP Exception Register  */
        uint64_t        fpr[PPC_NFPRS]; /*  Floating-Point Registers  */

        uint32_t        tbl;            /*  Time Base Lower  */
        uint32_t        tbu;            /*  Time Base Upper  */
        uint32_t        dec;            /*  Decrementer  */
        uint32_t        hdec;           /*  Hypervisor Decrementer  */
        uint64_t        sdr1;           /*  Storage Descriptor Register  */
        uint64_t        srr0;           /*  Supervisor save/restore 0  */
        uint64_t        srr1;           /*  Supervisor save/restore 1  */
        uint64_t        ssr0;           /*  Machine status save/restore
                                            register 0  */
        uint64_t        ssr1;           /*  Machine status save/restore
                                            register 1  */
        uint64_t        msr;            /*  Machine state register  */
        uint64_t        sprg0;          /*  Special Purpose Register G0  */
        uint64_t        sprg1;          /*  Special Purpose Register G1  */
        uint64_t        sprg2;          /*  Special Purpose Register G2  */
        uint64_t        sprg3;          /*  Special Purpose Register G3  */
        uint64_t        dbsr;           /*  Debug Status Register  */
        uint32_t        pvr;            /*  Processor Version Register  */
        uint32_t        pir;            /*  Processor ID  */

        /*  TODO: 64-bit SRs? (Segment registers)  */
        uint32_t        sr[16];

        /*  TODO: 64-bit BATs?  */
        uint32_t        ibat_u[4];
        uint32_t        ibat_l[4];
        uint32_t        dbat_u[4];
        uint32_t        dbat_l[4];

        uint64_t        ll_addr;        /*  Load-linked / store-conditional  */
        int             ll_bit;


        /*
         *  Instruction translation cache:
         */

        /*  cur_ic_page is a pointer to an array of PPC_IC_ENTRIES_PER_PAGE
            instruction call entries. next_ic points to the next such
            call to be executed.  */
        struct ppc_tc_physpage  *cur_physpage;
        struct ppc_instr_call   *cur_ic_page;
        struct ppc_instr_call   *next_ic;


        /*
         *  Virtual -> physical -> host address translation:
         *
         *  host_load and host_store point to arrays of PPC_N_VPH_ENTRIES
         *  pointers (to host pages); phys_addr points to an array of
         *  PPC_N_VPH_ENTRIES uint32_t.
         */

        struct ppc_vpg_tlb_entry        vph_tlb_entry[PPC_MAX_VPH_TLB_ENTRIES];
        unsigned char                   *host_load[PPC_N_VPH_ENTRIES]; 
        unsigned char                   *host_store[PPC_N_VPH_ENTRIES];
        uint32_t                        phys_addr[PPC_N_VPH_ENTRIES]; 
        struct ppc_tc_physpage          *phys_page[PPC_N_VPH_ENTRIES];

        uint32_t                        phystranslation[PPC_N_VPH_ENTRIES/32];
        int16_t                         vaddr_to_tlbindex[PPC_N_VPH_ENTRIES];
};


/*  Machine status word bits: (according to Book 3)  */
#define PPC_MSR_SF      (1ULL << 63)    /*  Sixty-Four-Bit Mode  */
/*  bits 62..61 are reserved  */
#define PPC_MSR_HV      (1ULL << 60)    /*  Hypervisor  */
/*  bits 59..17  are reserved  */
#define PPC_MSR_ILE     (1 << 16)       /*  Interrupt Little-Endian Mode  */
#define PPC_MSR_EE      (1 << 15)       /*  External Interrupt Enable  */
#define PPC_MSR_PR      (1 << 14)       /*  Problem State  */
#define PPC_MSR_FP      (1 << 13)       /*  Floating-Point Available  */
#define PPC_MSR_ME      (1 << 12)       /*  Machine Check Interrupt Enable  */
#define PPC_MSR_FE0     (1 << 11)       /*  Floating-Point Exception Mode 0  */
#define PPC_MSR_SE      (1 << 10)       /*  Single-Step Trace Enable  */
#define PPC_MSR_BE      (1 << 9)        /*  Branch Trace Enable  */
#define PPC_MSR_FE1     (1 << 8)        /*  Floating-Point Exception Mode 1  */
#define PPC_MSR_IR      (1 << 5)        /*  Instruction Relocate  */
#define PPC_MSR_DR      (1 << 4)        /*  Data Relocate  */
#define PPC_MSR_PMM     (1 << 2)        /*  Performance Monitor Mark  */
#define PPC_MSR_RI      (1 << 1)        /*  Recoverable Interrupt  */
#define PPC_MSR_LE      (1)             /*  Little-Endian Mode  */

/*  XER bits:  */
#define PPC_XER_SO      (1UL << 31)     /*  Summary Overflow  */
#define PPC_XER_OV      (1 << 30)       /*  Overflow  */
#define PPC_XER_CA      (1 << 29)       /*  Carry  */


/*  cpu_ppc.c:  */
void ppc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void ppc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void ppc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
void ppc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
void ppc_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
void ppc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
int ppc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
        unsigned char *data, size_t len, int writeflag, int cache_flags);
int ppc_cpu_family_init(struct cpu_family *);

/*  memory_ppc.c:  */
int ppc_translate_address(struct cpu *cpu, uint64_t vaddr,
        uint64_t *return_addr, int flags);

#endif  /*  CPU_PPC_H  */
1	dpavlin	4	#ifndef CPU_PPC_H
2			#define CPU_PPC_H
3
4			/*
5			* Copyright (C) 2005 Anders Gavare. All rights reserved.
6			*
7			* Redistribution and use in source and binary forms, with or without
8			* modification, are permitted provided that the following conditions are met:
9			*
10			* 1. Redistributions of source code must retain the above copyright
11			* notice, this list of conditions and the following disclaimer.
12			* 2. Redistributions in binary form must reproduce the above copyright
13			* notice, this list of conditions and the following disclaimer in the
14			* documentation and/or other materials provided with the distribution.
15			* 3. The name of the author may not be used to endorse or promote products
16			* derived from this software without specific prior written permission.
17			*
18			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28			* SUCH DAMAGE.
29			*
30			*
31	dpavlin	18	* $Id: cpu_ppc.h,v 1.41 2005/10/27 14:01:15 debug Exp $
32	dpavlin	4	*/
33
34			#include "misc.h"
35
36
37			struct cpu_family;
38
39			#define MODE_PPC 0
40			#define MODE_POWER 1
41
42			/* PPC CPU types: */
43			struct ppc_cpu_type_def {
44			char *name;
45	dpavlin	14	int pvr;
46	dpavlin	4	int bits;
47			int flags;
48			int icache_shift;
49	dpavlin	14	int ilinesize;
50	dpavlin	4	int iway;
51			int dcache_shift;
52	dpavlin	14	int dlinesize;
53	dpavlin	4	int dway;
54			int l2cache_shift;
55	dpavlin	14	int l2linesize;
56	dpavlin	4	int l2way;
57			int altivec;
58
59			/* TODO: POWER vs PowerPC? */
60			};
61
62			/* Flags: */
63			#define PPC_NOFP 1
64			/* TODO: Most of these just bogus */
65
66	dpavlin	14	#define PPC_CPU_TYPE_DEFS { \
67			{ "PPC405GP", 0, 32, PPC_NOFP, 15,5,2, 15,5,2, 20,5,1, 0 }, \
68			{ "PPC603e", 0, 32, 0, 14,5,4, 14,5,4, 0,0,0, 0 }, \
69			{ "MPC7400", 0x000c0000, 32, 0, 15,5,2, 15,5,2, 19,5,1, 1 }, \
70			{ "PPC750", 0x00084202, 32, 0, 15,5,2, 15,5,2, 20,5,1, 0 }, \
71			{ "G4e", 0, 32, 0, 15,5,8, 15,5,8, 18,5,8, 1 }, \
72			{ "PPC970", 0x00390000, 64, 0, 16,7,1, 15,7,2, 19,7,1, 1 }, \
73			{ NULL, 0, 0,0,0,0,0,0,0,0,0,0,0,0 } \
74			}
75	dpavlin	4
76			#define PPC_NGPRS 32
77			#define PPC_NFPRS 32
78
79	dpavlin	12
80			#define PPC_N_IC_ARGS 3
81			#define PPC_INSTR_ALIGNMENT_SHIFT 2
82			#define PPC_IC_ENTRIES_SHIFT 10
83			#define PPC_IC_ENTRIES_PER_PAGE (1 << PPC_IC_ENTRIES_SHIFT)
84			#define PPC_PC_TO_IC_ENTRY(a) (((a)>>PPC_INSTR_ALIGNMENT_SHIFT) \
85			& (PPC_IC_ENTRIES_PER_PAGE-1))
86			#define PPC_ADDR_TO_PAGENR(a) ((a) >> (PPC_IC_ENTRIES_SHIFT \
87			+ PPC_INSTR_ALIGNMENT_SHIFT))
88
89			struct ppc_instr_call {
90			void (f)(struct cpu , struct ppc_instr_call *);
91			size_t arg[PPC_N_IC_ARGS];
92			};
93
94			/* Translation cache struct for each physical page: */
95			struct ppc_tc_physpage {
96	dpavlin	18	struct ppc_instr_call ics[PPC_IC_ENTRIES_PER_PAGE + 1];
97	dpavlin	12	uint32_t next_ofs; /* or 0 for end of chain */
98	dpavlin	18	int flags;
99	dpavlin	12	uint64_t physaddr;
100			};
101
102			#define PPC_N_VPH_ENTRIES 1048576
103
104			#define PPC_MAX_VPH_TLB_ENTRIES 256
105			struct ppc_vpg_tlb_entry {
106			int valid;
107			int writeflag;
108			int64_t timestamp;
109			unsigned char *host_page;
110			uint64_t vaddr_page;
111			uint64_t paddr_page;
112			};
113
114	dpavlin	4	struct ppc_cpu {
115			struct ppc_cpu_type_def cpu_type;
116
117			uint64_t of_emul_addr;
118
119			int mode; /* MODE_PPC or MODE_POWER */
120			int bits; /* 32 or 64 */
121
122	dpavlin	12	uint64_t zero; /* A zero register */
123
124	dpavlin	4	uint32_t cr; /* Condition Register */
125			uint32_t fpscr; /* FP Status and Control Register */
126			uint64_t lr; /* Link Register */
127			uint64_t ctr; /* Count Register */
128			uint64_t gpr[PPC_NGPRS]; /* General Purpose Registers */
129			uint64_t xer; /* FP Exception Register */
130			uint64_t fpr[PPC_NFPRS]; /* Floating-Point Registers */
131
132			uint32_t tbl; /* Time Base Lower */
133			uint32_t tbu; /* Time Base Upper */
134			uint32_t dec; /* Decrementer */
135			uint32_t hdec; /* Hypervisor Decrementer */
136	dpavlin	14	uint64_t sdr1; /* Storage Descriptor Register */
137			uint64_t srr0; /* Supervisor save/restore 0 */
138			uint64_t srr1; /* Supervisor save/restore 1 */
139	dpavlin	4	uint64_t ssr0; /* Machine status save/restore
140			register 0 */
141			uint64_t ssr1; /* Machine status save/restore
142			register 1 */
143			uint64_t msr; /* Machine state register */
144			uint64_t sprg0; /* Special Purpose Register G0 */
145			uint64_t sprg1; /* Special Purpose Register G1 */
146			uint64_t sprg2; /* Special Purpose Register G2 */
147			uint64_t sprg3; /* Special Purpose Register G3 */
148	dpavlin	14	uint64_t dbsr; /* Debug Status Register */
149	dpavlin	4	uint32_t pvr; /* Processor Version Register */
150			uint32_t pir; /* Processor ID */
151	dpavlin	12
152	dpavlin	14	/* TODO: 64-bit SRs? (Segment registers) */
153			uint32_t sr[16];
154	dpavlin	12
155	dpavlin	14	/* TODO: 64-bit BATs? */
156			uint32_t ibat_u[4];
157			uint32_t ibat_l[4];
158			uint32_t dbat_u[4];
159			uint32_t dbat_l[4];
160
161			uint64_t ll_addr; /* Load-linked / store-conditional */
162			int ll_bit;
163
164
165	dpavlin	12	/*
166			* Instruction translation cache:
167			*/
168
169			/* cur_ic_page is a pointer to an array of PPC_IC_ENTRIES_PER_PAGE
170			instruction call entries. next_ic points to the next such
171			call to be executed. */
172			struct ppc_tc_physpage *cur_physpage;
173			struct ppc_instr_call *cur_ic_page;
174			struct ppc_instr_call *next_ic;
175
176
177			/*
178			* Virtual -> physical -> host address translation:
179			*
180			* host_load and host_store point to arrays of PPC_N_VPH_ENTRIES
181			* pointers (to host pages); phys_addr points to an array of
182			* PPC_N_VPH_ENTRIES uint32_t.
183			*/
184
185			struct ppc_vpg_tlb_entry vph_tlb_entry[PPC_MAX_VPH_TLB_ENTRIES];
186			unsigned char *host_load[PPC_N_VPH_ENTRIES];
187			unsigned char *host_store[PPC_N_VPH_ENTRIES];
188			uint32_t phys_addr[PPC_N_VPH_ENTRIES];
189			struct ppc_tc_physpage *phys_page[PPC_N_VPH_ENTRIES];
190	dpavlin	18
191			uint32_t phystranslation[PPC_N_VPH_ENTRIES/32];
192			int16_t vaddr_to_tlbindex[PPC_N_VPH_ENTRIES];
193	dpavlin	4	};
194
195
196			/* Machine status word bits: (according to Book 3) */
197			#define PPC_MSR_SF (1ULL << 63) /* Sixty-Four-Bit Mode */
198			/* bits 62..61 are reserved */
199			#define PPC_MSR_HV (1ULL << 60) /* Hypervisor */
200			/* bits 59..17 are reserved */
201			#define PPC_MSR_ILE (1 << 16) /* Interrupt Little-Endian Mode */
202			#define PPC_MSR_EE (1 << 15) /* External Interrupt Enable */
203			#define PPC_MSR_PR (1 << 14) /* Problem State */
204			#define PPC_MSR_FP (1 << 13) /* Floating-Point Available */
205			#define PPC_MSR_ME (1 << 12) /* Machine Check Interrupt Enable */
206			#define PPC_MSR_FE0 (1 << 11) /* Floating-Point Exception Mode 0 */
207			#define PPC_MSR_SE (1 << 10) /* Single-Step Trace Enable */
208			#define PPC_MSR_BE (1 << 9) /* Branch Trace Enable */
209			#define PPC_MSR_FE1 (1 << 8) /* Floating-Point Exception Mode 1 */
210			#define PPC_MSR_IR (1 << 5) /* Instruction Relocate */
211			#define PPC_MSR_DR (1 << 4) /* Data Relocate */
212			#define PPC_MSR_PMM (1 << 2) /* Performance Monitor Mark */
213			#define PPC_MSR_RI (1 << 1) /* Recoverable Interrupt */
214			#define PPC_MSR_LE (1) /* Little-Endian Mode */
215
216			/* XER bits: */
217	dpavlin	18	#define PPC_XER_SO (1UL << 31) /* Summary Overflow */
218	dpavlin	4	#define PPC_XER_OV (1 << 30) /* Overflow */
219			#define PPC_XER_CA (1 << 29) /* Carry */
220
221
222			/* cpu_ppc.c: */
223	dpavlin	12	void ppc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
224			unsigned char *host_page, int writeflag, uint64_t paddr_page);
225	dpavlin	14	void ppc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
226			unsigned char *host_page, int writeflag, uint64_t paddr_page);
227	dpavlin	18	void ppc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
228			void ppc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
229	dpavlin	14	void ppc_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
230			void ppc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
231	dpavlin	4	int ppc_memory_rw(struct cpu cpu, struct memory mem, uint64_t vaddr,
232			unsigned char *data, size_t len, int writeflag, int cache_flags);
233			int ppc_cpu_family_init(struct cpu_family *);
234
235	dpavlin	14	/* memory_ppc.c: */
236			int ppc_translate_address(struct cpu *cpu, uint64_t vaddr,
237			uint64_t *return_addr, int flags);
238	dpavlin	4
239			#endif /* CPU_PPC_H */