/[gxemul]/trunk/src/include/cpu_mips.h
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Contents of /trunk/src/include/cpu_mips.h

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Revision 28 - (show annotations)
Mon Oct 8 16:20:26 2007 UTC (13 years, 1 month ago) by dpavlin
File MIME type: text/plain
File size: 12004 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $
20060626	Continuing on SPARC emulation (beginning on the 'save'
		instruction, register windows, etc).
20060629	Planning statistics gathering (new -s command line option),
		and renaming speed_tricks to allow_instruction_combinations.
20060630	Some minor manual page updates.
		Various cleanups.
		Implementing the -s command line option.
20060701	FINALLY found the bug which prevented Linux and Ultrix from
		running without the ugly hack in the R2000/R3000 cache isol
		code; it was the phystranslation hint array which was buggy.
		Removing the phystranslation hint code completely, for now.
20060702	Minor dyntrans cleanups; invalidation of physpages now only
		invalidate those parts of a page that have actually been
		translated. (32 parts per page.)
		Some MIPS non-R3000 speed fixes.
		Experimenting with MIPS instruction combination for some
		addiu+bne+sw loops, and sw+sw+sw.
		Adding support (again) for larger-than-4KB pages in MIPS tlbw*.
		Continuing on SPARC emulation: adding load/store instructions.
20060704	Fixing a virtual vs physical page shift bug in the new tlbw*
		implementation. Problem noticed by Jakub Jermar. (Many thanks.)
		Moving rfe and eret to cpu_mips_instr.c, since that is the
		only place that uses them nowadays.
20060705	Removing the BSD license from the "testmachine" include files,
		placing them in the public domain instead; this enables the
		testmachine stuff to be used from projects which are
		incompatible with the BSD license for some reason.
20060707	Adding instruction combinations for the R2000/R3000 L1
		I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu,
		various branches followed by addiu or nop, and jr ra followed
		by addiu. The time it takes to perform a full NetBSD/pmax R3000
		install on the laptop has dropped from 573 seconds to 539. :-)
20060708	Adding a framebuffer controller device (dev_fbctrl), which so
		far can be used to change the fb resolution during runtime, but
		in the future will also be useful for accelerated block fill/
		copy, and possibly also simplified character output.
		Adding an instruction combination for NetBSD/pmax' strlen.
20060709	Minor fixes: reading raw files in src/file.c wasn't memblock
		aligned, removing buggy multi_sw MIPS instruction combination,
		etc.
20060711	Adding a machine_qemu.c, which contains a "qemu_mips" machine.
		(It mimics QEMU's MIPS machine mode, so that a test kernel
		made for QEMU_MIPS also can run in GXemul... at least to some
		extent.)  Adding a short section about how to run this mode to
		doc/guestoses.html.
20060714	Misc. minor code cleanups.
20060715	Applying a patch which adds getchar() to promemul/yamon.c
		(from Oleksandr Tymoshenko).
		Adding yamon.h from NetBSD, and rewriting yamon.c to use it
		(instead of ugly hardcoded numbers) + some cleanup.
20060716	Found and fixed the bug which broke single-stepping of 64-bit
		programs between 0.4.0 and 0.4.0.1 (caused by too quick
		refactoring and no testing). Hopefully this fix will not
		break too many other things.
20060718	Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS.
		Re-adding the sw+sw+sw instr comb (the problem was that I had
		ignored endian issues); however, it doesn't seem to give any
		big performance gain.
20060720	Adding a dummy Transputer mode (T414, T800 etc) skeleton (only
		the 'j' and 'ldc' instructions are implemented so far). :-}
20060721	Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus
		misc. other updates to get Linux 2.6 for evbmips/malta working
		(thanks to Alec Voropay for the details).
		FINALLY found and fixed the bug which made tlbw* for non-R3000
		buggy; it was a reference count problem in the dyntrans core.
20060722	Testing stuff; things seem stable enough for a new release.

==============  RELEASE 0.4.1  ==============


1 #ifndef CPU_MIPS_H
2 #define CPU_MIPS_H
3
4 /*
5 * Copyright (C) 2003-2006 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cpu_mips.h,v 1.45 2006/07/16 13:32:27 debug Exp $
32 */
33
34 #include "misc.h"
35
36 struct cpu_family;
37 struct emul;
38 struct machine;
39
40 /*
41 * CPU type definitions: See mips_cpu_types.h.
42 */
43
44 struct mips_cpu_type_def {
45 char *name;
46 int rev;
47 int sub;
48 char flags;
49 char exc_model; /* EXC3K or EXC4K */
50 char mmu_model; /* MMU3K or MMU4K */
51 char isa_level; /* 1, 2, 3, 4, 5, 32, 64 */
52 char isa_revision; /* 1 or 2 (for MIPS32/64) */
53 int nr_of_tlb_entries; /* 32, 48, 64, ... */
54 char instrs_per_cycle; /* simplified, 1, 2, or 4 */
55 int picache;
56 int pilinesize;
57 int piways;
58 int pdcache;
59 int pdlinesize;
60 int pdways;
61 int scache;
62 int slinesize;
63 int sways;
64 };
65
66 #define INITIAL_PC 0xffffffffbfc00000ULL
67 #define INITIAL_STACK_POINTER (0xffffffffa0008000ULL - 256)
68
69
70 /*
71 * Coproc 0:
72 *
73 * NOTE:
74 * On R3000, only hi and lo0 are used, and then only the lowest 32 bits.
75 */
76 #define N_MIPS_COPROC_REGS 32
77 struct mips_tlb {
78 uint64_t hi;
79 uint64_t lo0;
80 uint64_t lo1;
81 uint64_t mask;
82 };
83
84
85 /*
86 * Coproc 1:
87 */
88 /* FPU control registers: */
89 #define N_MIPS_FCRS 32
90 #define MIPS_FPU_FCIR 0
91 #define MIPS_FPU_FCCR 25
92 #define MIPS_FPU_FCSR 31
93 #define MIPS_FCSR_FCC0_SHIFT 23
94 #define MIPS_FCSR_FCC1_SHIFT 25
95
96 struct mips_coproc {
97 int coproc_nr;
98 uint64_t reg[N_MIPS_COPROC_REGS];
99
100 /* Only for COP0: */
101 struct mips_tlb *tlbs;
102 int nr_of_tlbs;
103
104 /* Only for COP1: floating point control registers */
105 /* (Maybe also for COP0?) */
106 uint64_t fcr[N_MIPS_FCRS];
107 };
108
109 #define N_MIPS_COPROCS 4
110
111 #define N_MIPS_GPRS 32 /* General purpose registers */
112 #define N_MIPS_FPRS 32 /* Floating point registers */
113
114 /*
115 * These should all be 2 characters wide:
116 *
117 * NOTE: These are for 32-bit ABIs. For the 64-bit ABI, registers 8..11
118 * are used to pass arguments and are then called "a4".."a7".
119 *
120 * TODO: Should there be two different variants of this? It's not really
121 * possible to figure out in some easy way if the code running was
122 * written for a 32-bit or 64-bit ABI.
123 */
124 #define MIPS_REGISTER_NAMES { \
125 "zr", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
126 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
127 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
128 "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra" }
129
130 #define MIPS_GPR_ZERO 0 /* zero */
131 #define MIPS_GPR_AT 1 /* at */
132 #define MIPS_GPR_V0 2 /* v0 */
133 #define MIPS_GPR_V1 3 /* v1 */
134 #define MIPS_GPR_A0 4 /* a0 */
135 #define MIPS_GPR_A1 5 /* a1 */
136 #define MIPS_GPR_A2 6 /* a2 */
137 #define MIPS_GPR_A3 7 /* a3 */
138 #define MIPS_GPR_T0 8 /* t0 */
139 #define MIPS_GPR_T1 9 /* t1 */
140 #define MIPS_GPR_T2 10 /* t2 */
141 #define MIPS_GPR_T3 11 /* t3 */
142 #define MIPS_GPR_T4 12 /* t4 */
143 #define MIPS_GPR_T5 13 /* t5 */
144 #define MIPS_GPR_T6 14 /* t6 */
145 #define MIPS_GPR_T7 15 /* t7 */
146 #define MIPS_GPR_S0 16 /* s0 */
147 #define MIPS_GPR_S1 17 /* s1 */
148 #define MIPS_GPR_S2 18 /* s2 */
149 #define MIPS_GPR_S3 19 /* s3 */
150 #define MIPS_GPR_S4 20 /* s4 */
151 #define MIPS_GPR_S5 21 /* s5 */
152 #define MIPS_GPR_S6 22 /* s6 */
153 #define MIPS_GPR_S7 23 /* s7 */
154 #define MIPS_GPR_T8 24 /* t8 */
155 #define MIPS_GPR_T9 25 /* t9 */
156 #define MIPS_GPR_K0 26 /* k0 */
157 #define MIPS_GPR_K1 27 /* k1 */
158 #define MIPS_GPR_GP 28 /* gp */
159 #define MIPS_GPR_SP 29 /* sp */
160 #define MIPS_GPR_FP 30 /* fp */
161 #define MIPS_GPR_RA 31 /* ra */
162
163 #define N_HI6 64
164 #define N_SPECIAL 64
165 #define N_REGIMM 32
166
167 /******************************* OLD: *****************************/
168
169 /* An "impossible" paddr: */
170 #define IMPOSSIBLE_PADDR 0x1212343456566767ULL
171
172 #define DEFAULT_PCACHE_SIZE 15 /* 32 KB */
173 #define DEFAULT_PCACHE_LINESIZE 5 /* 32 bytes */
174
175 struct r3000_cache_line {
176 uint32_t tag_paddr;
177 int tag_valid;
178 };
179 #define R3000_TAG_VALID 1
180 #define R3000_TAG_DIRTY 2
181
182 struct r4000_cache_line {
183 char dummy;
184 };
185
186 /********************************************************************/
187
188 #ifdef ONEKPAGE
189 #define MIPS_IC_ENTRIES_SHIFT 8
190 #else
191 #define MIPS_IC_ENTRIES_SHIFT 10
192 #endif
193
194 #define MIPS_N_IC_ARGS 3
195 #define MIPS_INSTR_ALIGNMENT_SHIFT 2
196 #define MIPS_IC_ENTRIES_PER_PAGE (1 << MIPS_IC_ENTRIES_SHIFT)
197 #define MIPS_PC_TO_IC_ENTRY(a) (((a)>>MIPS_INSTR_ALIGNMENT_SHIFT) \
198 & (MIPS_IC_ENTRIES_PER_PAGE-1))
199 #define MIPS_ADDR_TO_PAGENR(a) ((a) >> (MIPS_IC_ENTRIES_SHIFT \
200 + MIPS_INSTR_ALIGNMENT_SHIFT))
201
202 #define MIPS_L2N 17
203 #define MIPS_L3N 18
204
205 #define MIPS_MAX_VPH_TLB_ENTRIES 128
206 DYNTRANS_MISC_DECLARATIONS(mips,MIPS,uint64_t)
207 DYNTRANS_MISC64_DECLARATIONS(mips,MIPS,uint8_t)
208
209 #if 0
210 struct mips_instr_call {
211 void (*f)(struct cpu *, struct mips_instr_call *);
212 size_t arg[MIPS_N_IC_ARGS];
213 };
214
215 /* Translation cache struct for each physical page: */
216 struct mips_tc_physpage {
217 struct mips_instr_call ics[MIPS_IC_ENTRIES_PER_PAGE + 3];
218 uint32_t next_ofs; /* or 0 for end of chain */
219 int flags;
220 uint64_t physaddr;
221 };
222
223 struct mips_vpg_tlb_entry {
224 uint8_t valid;
225 uint8_t writeflag;
226 unsigned char *host_page;
227 int64_t timestamp;
228 uint64_t vaddr_page;
229 uint64_t paddr_page;
230 };
231 #endif
232
233 /********************************************************************/
234
235 struct mips_cpu {
236 struct mips_cpu_type_def cpu_type;
237
238 struct mips_coproc *coproc[N_MIPS_COPROCS];
239
240 int compare_register_set;
241
242 /* Special purpose registers: */
243 uint64_t hi;
244 uint64_t lo;
245
246 /* Dummy destination register when writing to the zero register: */
247 uint64_t scratch;
248
249 /* General purpose registers: */
250 uint64_t gpr[N_MIPS_GPRS];
251
252 int nullify_next; /* set to 1 if next instruction
253 is to be nullified */
254
255 int show_trace_delay; /* 0=normal, > 0 = delay until show_trace */
256 uint64_t show_trace_addr;
257
258 int last_was_jumptoself;
259 int jump_to_self_reg;
260
261 int rmw; /* Read-Modify-Write */
262 int rmw_len; /* Length of rmw modification */
263 uint64_t rmw_addr; /* Address of rmw modification */
264
265 /*
266 * NOTE: The R5900 has 128-bit registers. I'm not really sure
267 * whether they are used a lot or not, at least with code produced
268 * with gcc they are not. An important case however is lq and sq
269 * (load and store of 128-bit values). These "upper halves" of R5900
270 * quadwords can be used in those cases.
271 *
272 * hi1 and lo1 are the high 64-bit parts of the hi and lo registers.
273 * sa is a 32-bit "shift amount" register.
274 *
275 * TODO: Generalize this.
276 */
277 uint64_t gpr_quadhi[N_MIPS_GPRS];
278 uint64_t hi1;
279 uint64_t lo1;
280 uint32_t r5900_sa;
281
282
283 /* Data and Instruction caches: */
284 unsigned char *cache[2];
285 void *cache_tags[2];
286 uint64_t cache_last_paddr[2];
287 int cache_size[2];
288 int cache_linesize[2];
289 int cache_mask[2];
290 int cache_miss_penalty[2];
291
292 /* Other stuff: */
293 uint64_t cop0_config_select1;
294
295
296 /* NEW DYNTRANS: */
297
298
299 /*
300 * Instruction translation cache and Virtual->Physical->Host
301 * address translation:
302 */
303 DYNTRANS_ITC(mips)
304 VPH_TLBS(mips,MIPS)
305 VPH32(mips,MIPS,uint64_t,uint8_t)
306 VPH64(mips,MIPS,uint8_t)
307 };
308
309
310 /* cpu_mips.c: */
311 int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
312 void mips_cpu_tlbdump(struct machine *m, int x, int rawflag);
313 void mips_cpu_register_match(struct machine *m, char *name,
314 int writeflag, uint64_t *valuep, int *match_register);
315 void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs);
316 int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
317 int running, uint64_t addr);
318 int mips_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr);
319 int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr);
320 void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr,
321 /* uint64_t pagemask, */ int coproc_nr, uint64_t vaddr_vpn2,
322 int vaddr_asid, int x_64);
323 int mips_cpu_run(struct emul *emul, struct machine *machine);
324 void mips_cpu_dumpinfo(struct cpu *cpu);
325 void mips_cpu_list_available_types(void);
326 int mips_cpu_family_init(struct cpu_family *);
327
328
329 /* cpu_mips_coproc.c: */
330 struct mips_coproc *mips_coproc_new(struct cpu *cpu, int coproc_nr);
331 void mips_coproc_tlb_set_entry(struct cpu *cpu, int entrynr, int size,
332 uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,
333 int valid0, int valid1, int dirty0, int dirty1, int global, int asid,
334 int cachealgo0, int cachealgo1);
335 void coproc_register_read(struct cpu *cpu,
336 struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select);
337 void coproc_register_write(struct cpu *cpu,
338 struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int flag64,
339 int select);
340 void coproc_tlbpr(struct cpu *cpu, int readflag);
341 void coproc_tlbwri(struct cpu *cpu, int randomflag);
342 void coproc_rfe(struct cpu *cpu);
343 void coproc_eret(struct cpu *cpu);
344 void coproc_function(struct cpu *cpu, struct mips_coproc *cp, int cpnr,
345 uint32_t function, int unassemble_only, int running);
346
347
348 /* memory_mips.c: */
349 int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr,
350 int writeflag, size_t len, unsigned char *data);
351 int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
352 unsigned char *data, size_t len, int writeflag, int cache_flags);
353
354 int translate_v2p_mmu3k(struct cpu *cpu, uint64_t vaddr,
355 uint64_t *return_addr, int flags);
356 int translate_v2p_mmu8k(struct cpu *cpu, uint64_t vaddr,
357 uint64_t *return_addr, int flags);
358 int translate_v2p_mmu10k(struct cpu *cpu, uint64_t vaddr,
359 uint64_t *return_addr, int flags);
360 int translate_v2p_mmu4100(struct cpu *cpu, uint64_t vaddr,
361 uint64_t *return_addr, int flags);
362 int translate_v2p_generic(struct cpu *cpu, uint64_t vaddr,
363 uint64_t *return_addr, int flags);
364
365
366 /* Dyntrans unaligned load/store: */
367 void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic,
368 int is_left, int wlen, int store);
369
370
371 int mips_run_instr(struct cpu *cpu);
372 void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
373 unsigned char *host_page, int writeflag, uint64_t paddr_page);
374 void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
375 void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
376 int mips32_run_instr(struct cpu *cpu);
377 void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
378 unsigned char *host_page, int writeflag, uint64_t paddr_page);
379 void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
380 void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
381
382
383 #endif /* CPU_MIPS_H */

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