/[gxemul]/trunk/src/include/cpu_mips.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /trunk/src/include/cpu_mips.h

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Revision 34 - (show annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 11252 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============
1 #ifndef CPU_MIPS_H
2 #define CPU_MIPS_H
3
4 /*
5 * Copyright (C) 2003-2007 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cpu_mips.h,v 1.55 2007/02/07 18:58:32 debug Exp $
32 */
33
34 #include "interrupt.h"
35 #include "misc.h"
36
37 struct cpu_family;
38 struct emul;
39 struct machine;
40 struct timer;
41
42 /*
43 * CPU type definitions: See mips_cpu_types.h.
44 */
45
46 struct mips_cpu_type_def {
47 char *name;
48 int rev;
49 int sub;
50 char flags;
51 char exc_model; /* EXC3K or EXC4K */
52 char mmu_model; /* MMU3K or MMU4K */
53 char isa_level; /* 1, 2, 3, 4, 5, 32, 64 */
54 char isa_revision; /* 1 or 2 (for MIPS32/64) */
55 int nr_of_tlb_entries; /* 32, 48, 64, ... */
56 char instrs_per_cycle; /* simplified, 1, 2, or 4 */
57 int picache;
58 int pilinesize;
59 int piways;
60 int pdcache;
61 int pdlinesize;
62 int pdways;
63 int scache;
64 int slinesize;
65 int sways;
66 };
67
68 #define INITIAL_PC 0xffffffffbfc00000ULL
69 #define INITIAL_STACK_POINTER (0xffffffffa0008000ULL - 256)
70
71
72 /*
73 * Coproc 0:
74 *
75 * NOTE:
76 * On R3000, only hi and lo0 are used, and then only the lowest 32 bits.
77 */
78 #define N_MIPS_COPROC_REGS 32
79 struct mips_tlb {
80 uint64_t hi;
81 uint64_t lo0;
82 uint64_t lo1;
83 uint64_t mask;
84 };
85
86
87 /*
88 * Coproc 1:
89 */
90 /* FPU control registers: */
91 #define N_MIPS_FCRS 32
92 #define MIPS_FPU_FCIR 0
93 #define MIPS_FPU_FCCR 25
94 #define MIPS_FPU_FCSR 31
95 #define MIPS_FCSR_FCC0_SHIFT 23
96 #define MIPS_FCSR_FCC1_SHIFT 25
97
98 #define N_VADDR_TO_TLB_INDEX_ENTRIES (1 << 20)
99
100 struct mips_coproc {
101 int coproc_nr;
102 uint64_t reg[N_MIPS_COPROC_REGS];
103
104 /* Only for COP0: */
105 struct mips_tlb *tlbs;
106 int nr_of_tlbs;
107
108 /* Only for COP1: floating point control registers */
109 /* (Maybe also for COP0?) */
110 uint64_t fcr[N_MIPS_FCRS];
111 };
112
113 #define N_MIPS_COPROCS 4
114
115 #define N_MIPS_GPRS 32 /* General purpose registers */
116 #define N_MIPS_FPRS 32 /* Floating point registers */
117
118 /*
119 * These should all be 2 characters wide:
120 *
121 * NOTE: These are for 32-bit ABIs. For the 64-bit ABI, registers 8..11
122 * are used to pass arguments and are then called "a4".."a7".
123 *
124 * TODO: Should there be two different variants of this? It's not really
125 * possible to figure out in some easy way if the code running was
126 * written for a 32-bit or 64-bit ABI.
127 */
128 #define MIPS_REGISTER_NAMES { \
129 "zr", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
130 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
131 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
132 "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra" }
133
134 #define MIPS_GPR_ZERO 0 /* zero */
135 #define MIPS_GPR_AT 1 /* at */
136 #define MIPS_GPR_V0 2 /* v0 */
137 #define MIPS_GPR_V1 3 /* v1 */
138 #define MIPS_GPR_A0 4 /* a0 */
139 #define MIPS_GPR_A1 5 /* a1 */
140 #define MIPS_GPR_A2 6 /* a2 */
141 #define MIPS_GPR_A3 7 /* a3 */
142 #define MIPS_GPR_T0 8 /* t0 */
143 #define MIPS_GPR_T1 9 /* t1 */
144 #define MIPS_GPR_T2 10 /* t2 */
145 #define MIPS_GPR_T3 11 /* t3 */
146 #define MIPS_GPR_T4 12 /* t4 */
147 #define MIPS_GPR_T5 13 /* t5 */
148 #define MIPS_GPR_T6 14 /* t6 */
149 #define MIPS_GPR_T7 15 /* t7 */
150 #define MIPS_GPR_S0 16 /* s0 */
151 #define MIPS_GPR_S1 17 /* s1 */
152 #define MIPS_GPR_S2 18 /* s2 */
153 #define MIPS_GPR_S3 19 /* s3 */
154 #define MIPS_GPR_S4 20 /* s4 */
155 #define MIPS_GPR_S5 21 /* s5 */
156 #define MIPS_GPR_S6 22 /* s6 */
157 #define MIPS_GPR_S7 23 /* s7 */
158 #define MIPS_GPR_T8 24 /* t8 */
159 #define MIPS_GPR_T9 25 /* t9 */
160 #define MIPS_GPR_K0 26 /* k0 */
161 #define MIPS_GPR_K1 27 /* k1 */
162 #define MIPS_GPR_GP 28 /* gp */
163 #define MIPS_GPR_SP 29 /* sp */
164 #define MIPS_GPR_FP 30 /* fp */
165 #define MIPS_GPR_RA 31 /* ra */
166
167 #define N_HI6 64
168 #define N_SPECIAL 64
169 #define N_REGIMM 32
170
171
172 /* An "impossible" paddr: */
173 #define IMPOSSIBLE_PADDR 0x1212343456566767ULL
174
175 #define DEFAULT_PCACHE_SIZE 15 /* 32 KB */
176 #define DEFAULT_PCACHE_LINESIZE 5 /* 32 bytes */
177
178 struct r3000_cache_line {
179 uint32_t tag_paddr;
180 int tag_valid;
181 };
182 #define R3000_TAG_VALID 1
183 #define R3000_TAG_DIRTY 2
184
185 struct r4000_cache_line {
186 char dummy;
187 };
188
189
190 #ifdef ONEKPAGE
191 #define MIPS_IC_ENTRIES_SHIFT 8
192 #else
193 #define MIPS_IC_ENTRIES_SHIFT 10
194 #endif
195
196 #define MIPS_N_IC_ARGS 3
197 #define MIPS_INSTR_ALIGNMENT_SHIFT 2
198 #define MIPS_IC_ENTRIES_PER_PAGE (1 << MIPS_IC_ENTRIES_SHIFT)
199 #define MIPS_PC_TO_IC_ENTRY(a) (((a)>>MIPS_INSTR_ALIGNMENT_SHIFT) \
200 & (MIPS_IC_ENTRIES_PER_PAGE-1))
201 #define MIPS_ADDR_TO_PAGENR(a) ((a) >> (MIPS_IC_ENTRIES_SHIFT \
202 + MIPS_INSTR_ALIGNMENT_SHIFT))
203
204 #define MIPS_L2N 17
205 #define MIPS_L3N 18
206
207 #define MIPS_MAX_VPH_TLB_ENTRIES 128
208 DYNTRANS_MISC_DECLARATIONS(mips,MIPS,uint64_t)
209 DYNTRANS_MISC64_DECLARATIONS(mips,MIPS,uint8_t)
210
211
212 struct mips_cpu {
213 struct mips_cpu_type_def cpu_type;
214
215 /* General purpose registers: */
216 uint64_t gpr[N_MIPS_GPRS];
217
218 /* Dummy destination register when writing to the zero register: */
219 uint64_t scratch;
220
221 /* Special purpose registers: */
222 uint64_t hi;
223 uint64_t lo;
224
225 /* Coprocessors: */
226 struct mips_coproc *coproc[N_MIPS_COPROCS];
227 uint64_t cop0_config_select1;
228
229 int last_written_tlb_index;
230
231 /* Count/compare timer: */
232 int compare_register_set;
233 int compare_interrupts_pending;
234 struct interrupt irq_compare;
235 struct timer *timer;
236
237 int rmw; /* Read-Modify-Write */
238 int rmw_len; /* Length of rmw modification */
239 uint64_t rmw_addr; /* Address of rmw modification */
240
241 /*
242 * NOTE: The R5900 has 128-bit registers. I'm not really sure
243 * whether they are used a lot or not, at least with code produced
244 * with gcc they are not. An important case however is lq and sq
245 * (load and store of 128-bit values). These "upper halves" of R5900
246 * quadwords can be used in those cases.
247 *
248 * hi1 and lo1 are the high 64-bit parts of the hi and lo registers.
249 * sa is a 32-bit "shift amount" register.
250 *
251 * TODO: Generalize this.
252 */
253 uint64_t gpr_quadhi[N_MIPS_GPRS];
254 uint64_t hi1;
255 uint64_t lo1;
256 uint32_t r5900_sa;
257
258 /* Data and Instruction caches: */
259 unsigned char *cache[2];
260 void *cache_tags[2];
261 uint64_t cache_last_paddr[2];
262 int cache_size[2];
263 int cache_linesize[2];
264 int cache_mask[2];
265 int cache_miss_penalty[2];
266
267
268 /*
269 * Instruction translation cache and Virtual->Physical->Host
270 * address translation:
271 */
272 DYNTRANS_ITC(mips)
273 VPH_TLBS(mips,MIPS)
274 VPH32(mips,MIPS,uint64_t,uint8_t)
275 VPH64(mips,MIPS,uint8_t)
276 };
277
278
279 /* cpu_mips.c: */
280 void mips_cpu_interrupt_assert(struct interrupt *interrupt);
281 void mips_cpu_interrupt_deassert(struct interrupt *interrupt);
282 int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
283 void mips_cpu_tlbdump(struct machine *m, int x, int rawflag);
284 void mips_cpu_register_match(struct machine *m, char *name,
285 int writeflag, uint64_t *valuep, int *match_register);
286 void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs);
287 int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
288 int running, uint64_t addr);
289 void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr,
290 /* uint64_t pagemask, */ int coproc_nr, uint64_t vaddr_vpn2,
291 int vaddr_asid, int x_64);
292 int mips_cpu_run(struct emul *emul, struct machine *machine);
293 void mips_cpu_dumpinfo(struct cpu *cpu);
294 void mips_cpu_list_available_types(void);
295 int mips_cpu_family_init(struct cpu_family *);
296
297
298 /* cpu_mips_coproc.c: */
299 struct mips_coproc *mips_coproc_new(struct cpu *cpu, int coproc_nr);
300 void mips_coproc_tlb_set_entry(struct cpu *cpu, int entrynr, int size,
301 uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,
302 int valid0, int valid1, int dirty0, int dirty1, int global, int asid,
303 int cachealgo0, int cachealgo1);
304 void coproc_register_read(struct cpu *cpu,
305 struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select);
306 void coproc_register_write(struct cpu *cpu,
307 struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int flag64,
308 int select);
309 void coproc_tlbpr(struct cpu *cpu, int readflag);
310 void coproc_tlbwri(struct cpu *cpu, int randomflag);
311 void coproc_rfe(struct cpu *cpu);
312 void coproc_eret(struct cpu *cpu);
313 void coproc_function(struct cpu *cpu, struct mips_coproc *cp, int cpnr,
314 uint32_t function, int unassemble_only, int running);
315
316
317 /* memory_mips.c: */
318 int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr,
319 int writeflag, size_t len, unsigned char *data);
320 int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
321 unsigned char *data, size_t len, int writeflag, int cache_flags);
322
323 int translate_v2p_mmu3k(struct cpu *cpu, uint64_t vaddr,
324 uint64_t *return_addr, int flags);
325 int translate_v2p_mmu8k(struct cpu *cpu, uint64_t vaddr,
326 uint64_t *return_addr, int flags);
327 int translate_v2p_mmu10k(struct cpu *cpu, uint64_t vaddr,
328 uint64_t *return_addr, int flags);
329 int translate_v2p_mmu4100(struct cpu *cpu, uint64_t vaddr,
330 uint64_t *return_addr, int flags);
331 int translate_v2p_generic(struct cpu *cpu, uint64_t vaddr,
332 uint64_t *return_addr, int flags);
333
334
335 /* Dyntrans unaligned load/store: */
336 void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic,
337 int is_left, int wlen, int store);
338
339
340 int mips_run_instr(struct cpu *cpu);
341 void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
342 unsigned char *host_page, int writeflag, uint64_t paddr_page);
343 void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
344 void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
345 int mips32_run_instr(struct cpu *cpu);
346 void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
347 unsigned char *host_page, int writeflag, uint64_t paddr_page);
348 void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
349 void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
350
351
352 #endif /* CPU_MIPS_H */
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