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Revision Log
++ trunk/HISTORY (local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219 Various minor updates. Removing the old MIPS16 skeleton code,
because it will need to be rewritten for dyntrans anyway.
20060220-22 Removing the non-working dyntrans backend support.
Continuing on the 64-bit dyntrans virtual memory generalization.
20060223 More work on the 64-bit vm generalization.
20060225 Beginning on MIPS dyntrans load/store instructions.
Minor PPC updates (64-bit load/store, etc).
Fixes for the variable-instruction-length framework, some
minor AVR updates (a simple Hello World program works!).
Beginning on a skeleton for automatically generating documen-
tation (for devices etc.).
20060226 PPC updates (adding some more 64-bit instructions, etc).
AVR updates (more instructions).
FINALLY found and fixed the zs bug, making NetBSD/macppc
accept the serial console.
20060301 Adding more AVR instructions.
20060304 Continuing on AVR-related stuff. Beginning on a framework for
cycle-accurate device emulation. Adding an experimental "PAL
TV" device (just a dummy so far).
20060305 Adding more AVR instructions.
Adding a dummy epcom serial controller (for TS7200 emulation).
20060310 Removing the emul() command from configuration files, so only
net() and machine() are supported.
Minor progress on the MIPS dyntrans rewrite.
20060311 Continuing on the MIPS dyntrans rewrite (adding more
instructions, etc).
20060315 Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
beql, bnel, slti[u], various loads and stores).
20060316 Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
used.
Adding more MIPS dyntrans instructions, and fixing bugs.
20060318 Implementing fast loads/stores for MIPS dyntrans (big/little
endian, 32-bit and 64-bit modes).
20060320 Making MIPS dyntrans the default configure option; use
"--enable-oldmips" to use the old bintrans system.
Adding MIPS dyntrans dmult[u]; minor updates.
20060322 Continuing... adding some more instructions.
Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323 Moving src/debugger.c into a new directory (src/debugger/).
20060324 Fixing the hack used to load PPC ELFs (useful for relocated
Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26 Beginning to experiment with GDB remote serial protocol
connections; adding a -G command line option for selecting
which TCP port to listen to.
20060330 Beginning a major cleanup to replace things like "0x%016llx"
with more correct "0x%016"PRIx64, etc.
Continuing on the GDB remote serial protocol support.
20060331 More cleanup, and some minor GDB remote progress.
20060402 Adding a hack to the configure script, to allow compilation
on systems that lack PRIx64 etc.
20060406 Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
replacing it with a better fix from Olivier Houchard.
20060407 A remote debugger (gdb or ddd) can now start and stop the
emulator using the GDB remote serial protocol, and registers
and memory can be read. MIPS only for now.
20060408 More GDB progress: single-stepping also works, and also adding
support for ARM, PowerPC, and Alpha targets.
Continuing on the delay-slot-across-page-boundary issue.
20060412 Minor update: beginning to add support for the SPARC target
to the remote GDB functionality.
20060414 Various MIPS updates: adding more instructions for dyntrans
(eret, add), and making some exceptions work. Fixing a bug
in dmult[u].
Implementing the first SPARC instructions (sethi, or).
20060415 Adding "magic trap" instructions so that PROM calls can be
software emulated in MIPS dyntrans.
Adding more MIPS dyntrans instructions (ddiv, dadd) and
fixing another bug in dmult.
20060416 More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
rfi, an ugly hack for supporting R2000/R3000 style faked caches,
preliminary interrupt support, and various other updates and
bugfixes.
20060417 Adding more SPARC instructions (add, sub, sll[x], sra[x],
srl[x]), and useful SPARC header definitions.
Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
x86 updates related to variable instruction length stuff.
Adding unaligned loads/stores to the MIPS dyntrans mode (but
still using the pre-dyntrans (slow) imlementation).
20060419 Fixing a MIPS dyntrans exception-in-delay-slot bug.
Removing the old "show opcode statistics" functionality, since
it wasn't really useful and isn't implemented for dyntrans.
Single-stepping (or running with instruction trace) now looks
ok with dyntrans with delay-slot architectures.
20060420 Minor hacks (removing the -B command line option when compiled
for non-bintrans, and some other very minor updates).
Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422 Applying fixes for bugs discovered by Nils Weller's nwcc
(static DEC memmap => now per machine, and adding an extern
keyword in cpu_arm_instr.c).
Finally found one of the MIPS dyntrans bugs that I've been
looking for (copy/paste spelling error BIG vs LITTLE endian in
cpu_mips_instr_loadstore.c for 16-bit fast stores).
FINALLY found the major MIPS dyntrans bug: slti vs sltiu
signed/unsigned code in cpu_mips_instr.c. :-)
Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
NetBSD/hpcmips can now reach userland when using dyntrans :-)
Adding some more x86 dyntrans instructions.
Finally removed the old Alpha-specific virtual memory code,
and replaced it with the generic 64-bit version.
Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423 Continuing on the delay-slot-across-page-boundary issue;
adding an end_of_page2 ic slot (like I had planned before, but
had removed for some reason).
Adding a quick-and-dirty fallback to legacy coprocessor 1
code (i.e. skipping dyntrans implementation for now).
NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
R4400) can now be installed and run. :-) (Many bugs left
to fix, though.)
Adding more MIPS dyntrans instructions: madd[u], msub[u].
Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
maps somewhat (disassembly and dyntrans instruction decoding).
20060424 Adding an isa_revision field to mips_cpu_types.h, and making
sure that SPECIAL3 opcodes cause Reserved Instruction
exceptions on MIPS32/64 revisions lower than 2.
Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
instructions.
20060425 Removing the -m command line option ("run at most x
instructions") and -T ("single_step_on_bad_addr"), because
they never worked correctly with dyntrans anyway.
Freshening up the man page.
20060428 Adding more MIPS dyntrans instructions: bltzal[l], idle.
Enabling MIPS dyntrans compare interrupts.
20060429 FINALLY found the weird dyntrans bug, causing NetBSD etc. to
behave strangely: some floating point code (conditional
coprocessor branches) could not be reused from the old
non-dyntrans code. The "quick-and-dirty fallback" only appeared
to work. Fixing by implementing bc1* for MIPS dyntrans.
More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
Freshening up MIPS floating point disassembly appearance.
20060430 Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
"por" and "pextlw".
20060504 Disabling -u (userland emulation) unless compiled as unstable
development version.
Beginning on freshening up the testmachine include files,
to make it easier to reuse those files (placing them in
src/include/testmachine/), and beginning on a set of "demos"
or "tutorials" for the testmachine functionality.
Minor updates to the MIPS GDB remote protocol stub.
Refreshing doc/experiments.html and gdb_remote.html.
Enabling Alpha emulation in the stable release configuration,
even though no guest OSes for Alpha can run yet.
20060505 Adding a generic 'settings' object, which will contain
references to settable variables (which will later be possible
to access using the debugger).
20060506 Updating dev_disk and corresponding demo/documentation (and
switching from SCSI to IDE disk types, so it actually works
with current test machines :-).
20060510 Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
so that fseeko() doesn't give a warning.
Updating the section about how dyntrans works (the "runnable
IR") in doc/intro.html.
Instruction updates (some x64=1 checks, some more R5900
dyntrans stuff: better mul/mult separation from MIPS32/64,
adding ei and di).
Updating MIPS cpuregs.h to a newer one (from NetBSD).
Adding more MIPS dyntrans instructions: deret, ehb.
20060514 Adding disassembly and beginning implementation of SPARC wr
and wrpr instructions.
20060515 Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
machines. Adding the 32-bit "rd psr" instruction.
20060517 Disassembly support for the general SPARC rd instruction.
Partial implementation of the cmp (subcc) instruction.
Some other minor updates (making sure that R5900 processors
start up with the EIE bit enabled, otherwise Linux/playstation2
receives no interrupts).
20060519 Minor MIPS updates/cleanups.
20060521 Moving the MeshCube machine into evbmips; this seems to work
reasonably well with a snapshot of a NetBSD MeshCube kernel.
Cleanup/fix of MIPS config0 register initialization.
20060529 Minor MIPS fixes, including a sign-extension fix to the
unaligned load/store code, which makes NetBSD/pmax on R3000
work better with dyntrans. (Ultrix and Linux/DECstation still
don't work, though.)
20060530 Minor updates to the Alpha machine mode: adding an AlphaBook
mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531 Applying a bugfix for the MIPS dyntrans sc[d] instruction from
Ondrej Palkovsky. (Many thanks.)
20060601 Minifix to allow ARM immediate msr instruction to not give
an error for some valid values.
More Alpha updates.
20060602 Some minor Alpha updates.
20060603 Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
first boot messages :-) on an emulated Alphabook 1.
20060612 Minor updates; adding a dev_ether.h include file for the
testmachine ether device. Continuing the hunt for the dyntrans
bug which makes Linux and Ultrix on DECstation behave
strangely... FINALLY found it! It seems to be related to
invalidation of the translation cache, on tlbw{r,i}. There
also seems to be some remaining interrupt-related problems.
20060614 Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
(so that it uses 16 32-bit registers if the FR bit in the
status register is not set).
20060616 REMOVING BINTRANS COMPLETELY!
Removing the old MIPS interpretation mode.
Removing the MFHILO_DELAY and instruction delay stuff, because
they wouldn't work with dyntrans anyway.
20060617 Some documentation updates (adding "NetBSD-archive" to some
URLs, and new Debian/DECstation installation screenshots).
Removing the "tracenull" and "enable-caches" configure options.
Improving MIPS dyntrans performance somewhat (only invalidate
translations if necessary, on writes to the entryhi register,
instead of doing it for all cop0 writes).
20060618 More cleanup after the removal of the old MIPS emulation.
Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
only semi-successful so far (for R3000).
20060620 Minor update to allow clean compilation again on Tru64/Alpha.
20060622 MIPS cleanup and fixes (removing the pc_last stuff, which
doesn't make sense with dyntrans anyway, and fixing a cross-
page-delay-slot-with-exception case in end_of_page).
Removing the old max_random_cycles_per_chunk stuff, and the
concept of cycles vs instructions for MIPS emulation.
FINALLY found and fixed the bug which caused NetBSD/pmax
clocks to behave strangely (it was a load to the zero register,
which was treated as a NOP; now it is treated as a load to a
dummy scratch register).
20060623 Increasing the dyntrans chunk size back to
N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
Preparing for a quick release, even though there are known
bugs, and performance for non-R3000 MIPS emulation is very
poor. :-/
Reverting to half the dyntrans chunk size again, because
NetBSD/cats seemed less stable with full size chunks. :(
NetBSD/sgimips 3.0 can now run :-) (With release 0.3.8, only
NetBSD/sgimips 2.1 worked, not 3.0.)
============== RELEASE 0.4.0 ==============
| 1 | #ifndef CPU_MIPS_H |
| 2 | #define CPU_MIPS_H |
| 3 | |
| 4 | /* |
| 5 | * Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions are met: |
| 9 | * |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * 3. The name of the author may not be used to endorse or promote products |
| 16 | * derived from this software without specific prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 19 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 24 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 26 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 28 | * SUCH DAMAGE. |
| 29 | * |
| 30 | * |
| 31 | * $Id: cpu_mips.h,v 1.42 2006/06/22 13:22:41 debug Exp $ |
| 32 | */ |
| 33 | |
| 34 | #include "misc.h" |
| 35 | |
| 36 | struct cpu_family; |
| 37 | struct emul; |
| 38 | struct machine; |
| 39 | |
| 40 | /* |
| 41 | * CPU type definitions: See mips_cpu_types.h. |
| 42 | */ |
| 43 | |
| 44 | struct mips_cpu_type_def { |
| 45 | char *name; |
| 46 | int rev; |
| 47 | int sub; |
| 48 | char flags; |
| 49 | char exc_model; /* EXC3K or EXC4K */ |
| 50 | char mmu_model; /* MMU3K or MMU4K */ |
| 51 | char isa_level; /* 1, 2, 3, 4, 5, 32, 64 */ |
| 52 | char isa_revision; /* 1 or 2 (for MIPS32/64) */ |
| 53 | int nr_of_tlb_entries; /* 32, 48, 64, ... */ |
| 54 | char instrs_per_cycle; /* simplified, 1, 2, or 4 */ |
| 55 | int picache; |
| 56 | int pilinesize; |
| 57 | int piways; |
| 58 | int pdcache; |
| 59 | int pdlinesize; |
| 60 | int pdways; |
| 61 | int scache; |
| 62 | int slinesize; |
| 63 | int sways; |
| 64 | }; |
| 65 | |
| 66 | #define INITIAL_PC 0xffffffffbfc00000ULL |
| 67 | #define INITIAL_STACK_POINTER (0xffffffffa0008000ULL - 256) |
| 68 | |
| 69 | |
| 70 | /* |
| 71 | * Coproc 0: |
| 72 | */ |
| 73 | #define N_MIPS_COPROC_REGS 32 |
| 74 | struct mips_tlb { |
| 75 | uint64_t hi; |
| 76 | uint64_t lo0; |
| 77 | uint64_t lo1; |
| 78 | uint64_t mask; |
| 79 | }; |
| 80 | |
| 81 | |
| 82 | /* |
| 83 | * Coproc 1: |
| 84 | */ |
| 85 | /* FPU control registers: */ |
| 86 | #define N_MIPS_FCRS 32 |
| 87 | #define MIPS_FPU_FCIR 0 |
| 88 | #define MIPS_FPU_FCCR 25 |
| 89 | #define MIPS_FPU_FCSR 31 |
| 90 | #define MIPS_FCSR_FCC0_SHIFT 23 |
| 91 | #define MIPS_FCSR_FCC1_SHIFT 25 |
| 92 | |
| 93 | struct mips_coproc { |
| 94 | int coproc_nr; |
| 95 | uint64_t reg[N_MIPS_COPROC_REGS]; |
| 96 | |
| 97 | /* Only for COP0: */ |
| 98 | struct mips_tlb *tlbs; |
| 99 | int nr_of_tlbs; |
| 100 | |
| 101 | /* Only for COP1: floating point control registers */ |
| 102 | /* (Maybe also for COP0?) */ |
| 103 | uint64_t fcr[N_MIPS_FCRS]; |
| 104 | }; |
| 105 | |
| 106 | #define N_MIPS_COPROCS 4 |
| 107 | |
| 108 | #define N_MIPS_GPRS 32 /* General purpose registers */ |
| 109 | #define N_MIPS_FPRS 32 /* Floating point registers */ |
| 110 | |
| 111 | /* |
| 112 | * These should all be 2 characters wide: |
| 113 | * |
| 114 | * NOTE: These are for 32-bit ABIs. For the 64-bit ABI, registers 8..11 |
| 115 | * are used to pass arguments and are then called "a4".."a7". |
| 116 | * |
| 117 | * TODO: Should there be two different variants of this? It's not really |
| 118 | * possible to figure out in some easy way if the code running was |
| 119 | * written for a 32-bit or 64-bit ABI. |
| 120 | */ |
| 121 | #define MIPS_REGISTER_NAMES { \ |
| 122 | "zr", "at", "v0", "v1", "a0", "a1", "a2", "a3", \ |
| 123 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \ |
| 124 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \ |
| 125 | "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra" } |
| 126 | |
| 127 | #define MIPS_GPR_ZERO 0 /* zero */ |
| 128 | #define MIPS_GPR_AT 1 /* at */ |
| 129 | #define MIPS_GPR_V0 2 /* v0 */ |
| 130 | #define MIPS_GPR_V1 3 /* v1 */ |
| 131 | #define MIPS_GPR_A0 4 /* a0 */ |
| 132 | #define MIPS_GPR_A1 5 /* a1 */ |
| 133 | #define MIPS_GPR_A2 6 /* a2 */ |
| 134 | #define MIPS_GPR_A3 7 /* a3 */ |
| 135 | #define MIPS_GPR_T0 8 /* t0 */ |
| 136 | #define MIPS_GPR_T1 9 /* t1 */ |
| 137 | #define MIPS_GPR_T2 10 /* t2 */ |
| 138 | #define MIPS_GPR_T3 11 /* t3 */ |
| 139 | #define MIPS_GPR_T4 12 /* t4 */ |
| 140 | #define MIPS_GPR_T5 13 /* t5 */ |
| 141 | #define MIPS_GPR_T6 14 /* t6 */ |
| 142 | #define MIPS_GPR_T7 15 /* t7 */ |
| 143 | #define MIPS_GPR_S0 16 /* s0 */ |
| 144 | #define MIPS_GPR_S1 17 /* s1 */ |
| 145 | #define MIPS_GPR_S2 18 /* s2 */ |
| 146 | #define MIPS_GPR_S3 19 /* s3 */ |
| 147 | #define MIPS_GPR_S4 20 /* s4 */ |
| 148 | #define MIPS_GPR_S5 21 /* s5 */ |
| 149 | #define MIPS_GPR_S6 22 /* s6 */ |
| 150 | #define MIPS_GPR_S7 23 /* s7 */ |
| 151 | #define MIPS_GPR_T8 24 /* t8 */ |
| 152 | #define MIPS_GPR_T9 25 /* t9 */ |
| 153 | #define MIPS_GPR_K0 26 /* k0 */ |
| 154 | #define MIPS_GPR_K1 27 /* k1 */ |
| 155 | #define MIPS_GPR_GP 28 /* gp */ |
| 156 | #define MIPS_GPR_SP 29 /* sp */ |
| 157 | #define MIPS_GPR_FP 30 /* fp */ |
| 158 | #define MIPS_GPR_RA 31 /* ra */ |
| 159 | |
| 160 | #define N_HI6 64 |
| 161 | #define N_SPECIAL 64 |
| 162 | #define N_REGIMM 32 |
| 163 | |
| 164 | /******************************* OLD: *****************************/ |
| 165 | |
| 166 | /* An "impossible" paddr: */ |
| 167 | #define IMPOSSIBLE_PADDR 0x1212343456566767ULL |
| 168 | |
| 169 | #define DEFAULT_PCACHE_SIZE 15 /* 32 KB */ |
| 170 | #define DEFAULT_PCACHE_LINESIZE 5 /* 32 bytes */ |
| 171 | |
| 172 | struct r3000_cache_line { |
| 173 | uint32_t tag_paddr; |
| 174 | int tag_valid; |
| 175 | }; |
| 176 | #define R3000_TAG_VALID 1 |
| 177 | #define R3000_TAG_DIRTY 2 |
| 178 | |
| 179 | struct r4000_cache_line { |
| 180 | char dummy; |
| 181 | }; |
| 182 | |
| 183 | /********************************************************************/ |
| 184 | |
| 185 | #ifdef ONEKPAGE |
| 186 | #define MIPS_IC_ENTRIES_SHIFT 8 |
| 187 | #else |
| 188 | #define MIPS_IC_ENTRIES_SHIFT 10 |
| 189 | #endif |
| 190 | |
| 191 | #define MIPS_N_IC_ARGS 3 |
| 192 | #define MIPS_INSTR_ALIGNMENT_SHIFT 2 |
| 193 | #define MIPS_IC_ENTRIES_PER_PAGE (1 << MIPS_IC_ENTRIES_SHIFT) |
| 194 | #define MIPS_PC_TO_IC_ENTRY(a) (((a)>>MIPS_INSTR_ALIGNMENT_SHIFT) \ |
| 195 | & (MIPS_IC_ENTRIES_PER_PAGE-1)) |
| 196 | #define MIPS_ADDR_TO_PAGENR(a) ((a) >> (MIPS_IC_ENTRIES_SHIFT \ |
| 197 | + MIPS_INSTR_ALIGNMENT_SHIFT)) |
| 198 | |
| 199 | #define MIPS_L2N 17 |
| 200 | #define MIPS_L3N 18 |
| 201 | |
| 202 | #define MIPS_MAX_VPH_TLB_ENTRIES 128 |
| 203 | DYNTRANS_MISC_DECLARATIONS(mips,MIPS,uint64_t) |
| 204 | DYNTRANS_MISC64_DECLARATIONS(mips,MIPS,uint8_t) |
| 205 | |
| 206 | #if 0 |
| 207 | struct mips_instr_call { |
| 208 | void (*f)(struct cpu *, struct mips_instr_call *); |
| 209 | size_t arg[MIPS_N_IC_ARGS]; |
| 210 | }; |
| 211 | |
| 212 | /* Translation cache struct for each physical page: */ |
| 213 | struct mips_tc_physpage { |
| 214 | struct mips_instr_call ics[MIPS_IC_ENTRIES_PER_PAGE + 3]; |
| 215 | uint32_t next_ofs; /* or 0 for end of chain */ |
| 216 | int flags; |
| 217 | uint64_t physaddr; |
| 218 | }; |
| 219 | |
| 220 | struct mips_vpg_tlb_entry { |
| 221 | uint8_t valid; |
| 222 | uint8_t writeflag; |
| 223 | unsigned char *host_page; |
| 224 | int64_t timestamp; |
| 225 | uint64_t vaddr_page; |
| 226 | uint64_t paddr_page; |
| 227 | }; |
| 228 | #endif |
| 229 | |
| 230 | /********************************************************************/ |
| 231 | |
| 232 | struct mips_cpu { |
| 233 | struct mips_cpu_type_def cpu_type; |
| 234 | |
| 235 | struct mips_coproc *coproc[N_MIPS_COPROCS]; |
| 236 | |
| 237 | int compare_register_set; |
| 238 | |
| 239 | /* Special purpose registers: */ |
| 240 | uint64_t hi; |
| 241 | uint64_t lo; |
| 242 | |
| 243 | /* Dummy destination register when writing to the zero register: */ |
| 244 | uint64_t scratch; |
| 245 | |
| 246 | /* General purpose registers: */ |
| 247 | uint64_t gpr[N_MIPS_GPRS]; |
| 248 | |
| 249 | int nullify_next; /* set to 1 if next instruction |
| 250 | is to be nullified */ |
| 251 | |
| 252 | int show_trace_delay; /* 0=normal, > 0 = delay until show_trace */ |
| 253 | uint64_t show_trace_addr; |
| 254 | |
| 255 | int last_was_jumptoself; |
| 256 | int jump_to_self_reg; |
| 257 | |
| 258 | int rmw; /* Read-Modify-Write */ |
| 259 | int rmw_len; /* Length of rmw modification */ |
| 260 | uint64_t rmw_addr; /* Address of rmw modification */ |
| 261 | |
| 262 | /* |
| 263 | * NOTE: The R5900 has 128-bit registers. I'm not really sure |
| 264 | * whether they are used a lot or not, at least with code produced |
| 265 | * with gcc they are not. An important case however is lq and sq |
| 266 | * (load and store of 128-bit values). These "upper halves" of R5900 |
| 267 | * quadwords can be used in those cases. |
| 268 | * |
| 269 | * hi1 and lo1 are the high 64-bit parts of the hi and lo registers. |
| 270 | * sa is a 32-bit "shift amount" register. |
| 271 | * |
| 272 | * TODO: Generalize this. |
| 273 | */ |
| 274 | uint64_t gpr_quadhi[N_MIPS_GPRS]; |
| 275 | uint64_t hi1; |
| 276 | uint64_t lo1; |
| 277 | uint32_t r5900_sa; |
| 278 | |
| 279 | |
| 280 | /* Data and Instruction caches: */ |
| 281 | unsigned char *cache[2]; |
| 282 | void *cache_tags[2]; |
| 283 | uint64_t cache_last_paddr[2]; |
| 284 | int cache_size[2]; |
| 285 | int cache_linesize[2]; |
| 286 | int cache_mask[2]; |
| 287 | int cache_miss_penalty[2]; |
| 288 | |
| 289 | /* Other stuff: */ |
| 290 | uint64_t cop0_config_select1; |
| 291 | |
| 292 | |
| 293 | /* NEW DYNTRANS: */ |
| 294 | |
| 295 | |
| 296 | /* |
| 297 | * Instruction translation cache and Virtual->Physical->Host |
| 298 | * address translation: |
| 299 | */ |
| 300 | DYNTRANS_ITC(mips) |
| 301 | VPH_TLBS(mips,MIPS) |
| 302 | VPH32(mips,MIPS,uint64_t,uint8_t) |
| 303 | VPH64(mips,MIPS,uint8_t) |
| 304 | }; |
| 305 | |
| 306 | |
| 307 | /* cpu_mips.c: */ |
| 308 | int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib); |
| 309 | void mips_cpu_tlbdump(struct machine *m, int x, int rawflag); |
| 310 | void mips_cpu_register_match(struct machine *m, char *name, |
| 311 | int writeflag, uint64_t *valuep, int *match_register); |
| 312 | void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs); |
| 313 | int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
| 314 | int running, uint64_t addr); |
| 315 | int mips_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr); |
| 316 | int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr); |
| 317 | void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr, |
| 318 | /* uint64_t pagemask, */ int coproc_nr, uint64_t vaddr_vpn2, |
| 319 | int vaddr_asid, int x_64); |
| 320 | int mips_cpu_run(struct emul *emul, struct machine *machine); |
| 321 | void mips_cpu_dumpinfo(struct cpu *cpu); |
| 322 | void mips_cpu_list_available_types(void); |
| 323 | int mips_cpu_family_init(struct cpu_family *); |
| 324 | |
| 325 | |
| 326 | /* cpu_mips_coproc.c: */ |
| 327 | struct mips_coproc *mips_coproc_new(struct cpu *cpu, int coproc_nr); |
| 328 | void mips_coproc_tlb_set_entry(struct cpu *cpu, int entrynr, int size, |
| 329 | uint64_t vaddr, uint64_t paddr0, uint64_t paddr1, |
| 330 | int valid0, int valid1, int dirty0, int dirty1, int global, int asid, |
| 331 | int cachealgo0, int cachealgo1); |
| 332 | void coproc_register_read(struct cpu *cpu, |
| 333 | struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select); |
| 334 | void coproc_register_write(struct cpu *cpu, |
| 335 | struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int flag64, |
| 336 | int select); |
| 337 | void coproc_tlbpr(struct cpu *cpu, int readflag); |
| 338 | void coproc_tlbwri(struct cpu *cpu, int randomflag); |
| 339 | void coproc_rfe(struct cpu *cpu); |
| 340 | void coproc_eret(struct cpu *cpu); |
| 341 | void coproc_function(struct cpu *cpu, struct mips_coproc *cp, int cpnr, |
| 342 | uint32_t function, int unassemble_only, int running); |
| 343 | |
| 344 | |
| 345 | /* memory_mips.c: */ |
| 346 | int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr, |
| 347 | int writeflag, size_t len, unsigned char *data); |
| 348 | int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
| 349 | unsigned char *data, size_t len, int writeflag, int cache_flags); |
| 350 | |
| 351 | |
| 352 | /* Dyntrans unaligned load/store: */ |
| 353 | void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic, |
| 354 | int is_left, int wlen, int store); |
| 355 | |
| 356 | |
| 357 | void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
| 358 | unsigned char *host_page, int writeflag, uint64_t paddr_page); |
| 359 | void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
| 360 | void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
| 361 | void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
| 362 | unsigned char *host_page, int writeflag, uint64_t paddr_page); |
| 363 | void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
| 364 | void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
| 365 | void mips_init_64bit_dummy_tables(struct cpu *cpu); |
| 366 | |
| 367 | |
| 368 | #endif /* CPU_MIPS_H */ |
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