/[gxemul]/trunk/src/include/cpu_mips.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC revision 24 by dpavlin, Mon Oct 8 16:19:56 2007 UTC
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_mips.h,v 1.26 2006/02/13 04:23:25 debug Exp $   *  $Id: cpu_mips.h,v 1.42 2006/06/22 13:22:41 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
35    
 /*    
  *  ENABLE_MIPS16 should be defined on the cc commandline using -D, if you  
  *  want it. (This is done by ./configure --mips16)  
  */  
 /*  #define MFHILO_DELAY  */  
   
36  struct cpu_family;  struct cpu_family;
37  struct emul;  struct emul;
38  struct machine;  struct machine;
# Line 55  struct mips_cpu_type_def { Line 49  struct mips_cpu_type_def {
49          char            exc_model;              /*  EXC3K or EXC4K  */          char            exc_model;              /*  EXC3K or EXC4K  */
50          char            mmu_model;              /*  MMU3K or MMU4K  */          char            mmu_model;              /*  MMU3K or MMU4K  */
51          char            isa_level;              /*  1, 2, 3, 4, 5, 32, 64  */          char            isa_level;              /*  1, 2, 3, 4, 5, 32, 64  */
52            char            isa_revision;           /*  1 or 2 (for MIPS32/64)  */
53          int             nr_of_tlb_entries;      /*  32, 48, 64, ...  */          int             nr_of_tlb_entries;      /*  32, 48, 64, ...  */
54          char            instrs_per_cycle;       /*  simplified, 1, 2, or 4  */          char            instrs_per_cycle;       /*  simplified, 1, 2, or 4  */
55          int             picache;          int             picache;
# Line 87  struct mips_tlb { Line 82  struct mips_tlb {
82  /*  /*
83   *  Coproc 1:   *  Coproc 1:
84   */   */
85  #define N_MIPS_FCRS             32  /*  FPU control registers:  */
86    #define N_MIPS_FCRS                     32
87    #define MIPS_FPU_FCIR                   0
88    #define MIPS_FPU_FCCR                   25
89    #define MIPS_FPU_FCSR                   31
90    #define    MIPS_FCSR_FCC0_SHIFT            23
91    #define    MIPS_FCSR_FCC1_SHIFT            25
92    
93  struct mips_coproc {  struct mips_coproc {
94          int             coproc_nr;          int             coproc_nr;
# Line 156  struct mips_coproc { Line 157  struct mips_coproc {
157  #define MIPS_GPR_FP             30              /*  fp  */  #define MIPS_GPR_FP             30              /*  fp  */
158  #define MIPS_GPR_RA             31              /*  ra  */  #define MIPS_GPR_RA             31              /*  ra  */
159    
 /*  Meaning of delay_slot:  */  
 #define NOT_DELAYED                     0  
 #define DELAYED                         1  
 #define TO_BE_DELAYED                   2  
 #define EXCEPTION_IN_DELAY_SLOT         0x100  
   
160  #define N_HI6                   64  #define N_HI6                   64
161  #define N_SPECIAL               64  #define N_SPECIAL               64
162  #define N_REGIMM                32  #define N_REGIMM                32
163    
164  /*******************************  OLD:  *****************************/  /*******************************  OLD:  *****************************/
165    
 /*  Number of "tiny" translation cache entries:  */  
 #define N_TRANSLATION_CACHE_INSTR       5  
 #define N_TRANSLATION_CACHE_DATA        5  
   
 struct translation_cache_entry {  
         int             wf;  
         uint64_t        vaddr_pfn;  
         uint64_t        paddr;  
 };  
   
 /*  This should be a value which the program counter  
     can "never" have:  */  
 #define PC_LAST_PAGE_IMPOSSIBLE_VALUE   3  
   
166  /*  An "impossible" paddr:  */  /*  An "impossible" paddr:  */
167  #define IMPOSSIBLE_PADDR                0x1212343456566767ULL  #define IMPOSSIBLE_PADDR                0x1212343456566767ULL
168    
# Line 215  struct r4000_cache_line { Line 196  struct r4000_cache_line {
196  #define MIPS_ADDR_TO_PAGENR(a)          ((a) >> (MIPS_IC_ENTRIES_SHIFT \  #define MIPS_ADDR_TO_PAGENR(a)          ((a) >> (MIPS_IC_ENTRIES_SHIFT \
197                                          + MIPS_INSTR_ALIGNMENT_SHIFT))                                          + MIPS_INSTR_ALIGNMENT_SHIFT))
198    
199    #define MIPS_L2N                17
200    #define MIPS_L3N                18
201    
202    #define MIPS_MAX_VPH_TLB_ENTRIES        128
203    DYNTRANS_MISC_DECLARATIONS(mips,MIPS,uint64_t)
204    DYNTRANS_MISC64_DECLARATIONS(mips,MIPS,uint8_t)
205    
206    #if 0
207  struct mips_instr_call {  struct mips_instr_call {
208          void    (*f)(struct cpu *, struct mips_instr_call *);          void    (*f)(struct cpu *, struct mips_instr_call *);
209          size_t  arg[MIPS_N_IC_ARGS];          size_t  arg[MIPS_N_IC_ARGS];
# Line 228  struct mips_tc_physpage { Line 217  struct mips_tc_physpage {
217          uint64_t        physaddr;          uint64_t        physaddr;
218  };  };
219    
 #define MIPS_MAX_VPH_TLB_ENTRIES        128  
220  struct mips_vpg_tlb_entry {  struct mips_vpg_tlb_entry {
221          uint8_t         valid;          uint8_t         valid;
222          uint8_t         writeflag;          uint8_t         writeflag;
# Line 237  struct mips_vpg_tlb_entry { Line 225  struct mips_vpg_tlb_entry {
225          uint64_t        vaddr_page;          uint64_t        vaddr_page;
226          uint64_t        paddr_page;          uint64_t        paddr_page;
227  };  };
228    #endif
   
 /*******************************  OLD:  *****************************/  
   
 #define BINTRANS_DONT_RUN_NEXT          0x1000000  
 #define BINTRANS_N_MASK                 0x0ffffff  
   
 #define N_SAFE_BINTRANS_LIMIT_SHIFT     14  
 #define N_SAFE_BINTRANS_LIMIT   ((1 << (N_SAFE_BINTRANS_LIMIT_SHIFT - 1)) - 1)  
   
 #define N_BINTRANS_VADDR_TO_HOST        20  
   
 /*  Virtual to host address translation tables:  */  
 struct vth32_table {  
         void                    *haddr_entry[1024 * 2];  
         uint32_t                paddr_entry[1024];  
         uint32_t                *bintrans_chunks[1024];  
         struct vth32_table      *next_free;  
         int                     refcount;  
 };  
229    
230  /********************************************************************/  /********************************************************************/
231    
# Line 268  struct mips_cpu { Line 237  struct mips_cpu {
237          int             compare_register_set;          int             compare_register_set;
238    
239          /*  Special purpose registers:  */          /*  Special purpose registers:  */
         uint64_t        pc_last;                /*  PC of last instruction   */  
240          uint64_t        hi;          uint64_t        hi;
241          uint64_t        lo;          uint64_t        lo;
242    
243            /*  Dummy destination register when writing to the zero register:  */
244            uint64_t        scratch;
245    
246          /*  General purpose registers:  */          /*  General purpose registers:  */
247          uint64_t        gpr[N_MIPS_GPRS];          uint64_t        gpr[N_MIPS_GPRS];
248    
         /*  
          *  The translation_cached stuff is used to speed up the  
          *  most recent lookups into the TLB.  Whenever the TLB is  
          *  written to, translation_cached[] must be filled with zeros.  
          */  
 #ifdef USE_TINY_CACHE  
         struct translation_cache_entry  
                         translation_cache_instr[N_TRANSLATION_CACHE_INSTR];  
         struct translation_cache_entry  
                         translation_cache_data[N_TRANSLATION_CACHE_DATA];  
 #endif  
   
         /*  
          *  For faster memory lookup when running instructions:  
          *  
          *  Reading memory to load instructions is a very common thing in the  
          *  emulator, and an instruction is very often read from the address  
          *  following the previously executed instruction. That means that we  
          *  don't have to go through the TLB each time.  
          *  
          *  We then get the vaddr -> paddr translation for free. There is an  
          *  even better case when the paddr is a RAM address (as opposed to an  
          *  address in a memory mapped device). Then we can figure out the  
          *  address in the host's memory directly, and skip the paddr -> host  
          *  address calculation as well.  
          *  
          *  A modification to the TLB should set the virtual_page variable to  
          *  an "impossible" value, so that there won't be a hit on the next  
          *  instruction.  
          */  
         uint64_t        pc_last_virtual_page;  
         uint64_t        pc_last_physical_page;  
         unsigned char   *pc_last_host_4k_page;  
   
         /*  MIPS Bintrans:  */  
         int             dont_run_next_bintrans;  
         int             bintrans_instructions_executed;  /*  set to the  
                                 number of bintranslated instructions executed  
                                 when running a bintrans codechunk  */  
         int             pc_bintrans_paddr_valid;  
         uint64_t        pc_bintrans_paddr;  
         unsigned char   *pc_bintrans_host_4kpage;  
   
         /*  Chunk base address:  */  
         unsigned char   *chunk_base_address;  
   
         /*  This should work for 32-bit MIPS emulation:  */  
         struct vth32_table *vaddr_to_hostaddr_nulltable;  
         struct vth32_table *vaddr_to_hostaddr_r2k3k_icachetable;  
         struct vth32_table *vaddr_to_hostaddr_r2k3k_dcachetable;  
         struct vth32_table **vaddr_to_hostaddr_table0_kernel;  
         struct vth32_table **vaddr_to_hostaddr_table0_cacheisol_i;  
         struct vth32_table **vaddr_to_hostaddr_table0_cacheisol_d;  
         struct vth32_table **vaddr_to_hostaddr_table0_user;  
         struct vth32_table **vaddr_to_hostaddr_table0;  /*  should point to kernel or user  */  
         struct vth32_table *next_free_vth_table;  
   
 /*  Testing...  */  
         unsigned char   **host_OLD_load;  
         unsigned char   **host_OLD_store;  
         unsigned char   **host_load_orig;  
         unsigned char   **host_store_orig;  
         unsigned char   **huge_r2k3k_cache_table;  
   
         /*  For 64-bit (generic) emulation:  */  
         unsigned char   *(*fast_vaddr_to_hostaddr)(struct cpu *cpu,  
                             uint64_t vaddr, int writeflag);  
         int             bintrans_next_index;  
         int             bintrans_data_writable[N_BINTRANS_VADDR_TO_HOST];  
         uint64_t        bintrans_data_vaddr[N_BINTRANS_VADDR_TO_HOST];  
         unsigned char   *bintrans_data_hostpage[N_BINTRANS_VADDR_TO_HOST];  
   
         void            (*bintrans_load_32bit)(struct cpu *);   /*  Note: incorrect args  */  
         void            (*bintrans_store_32bit)(struct cpu *);  /*  Note: incorrect args  */  
         void            (*bintrans_jump_to_32bit_pc)(struct cpu *);  
         void            (*bintrans_simple_exception)(struct cpu *, int);  
         void            (*bintrans_fast_rfe)(struct cpu *);  
         void            (*bintrans_fast_eret)(struct cpu *);  
         void            (*bintrans_fast_tlbwri)(struct cpu *, int);  
         void            (*bintrans_fast_tlbpr)(struct cpu *, int);  
   
 #ifdef ENABLE_MIPS16  
         int             mips16;                 /*  non-zero if MIPS16 code is allowed  */  
         uint16_t        mips16_extend;          /*  set on 'extend' instructions to the entire 16-bit extend instruction  */  
 #endif  
   
 #ifdef ENABLE_INSTRUCTION_DELAYS  
         int             instruction_delay;  
 #endif  
   
         uint64_t        delay_jmpaddr;          /*  only used if delay_slot > 0  */  
         int             delay_slot;  
249          int             nullify_next;           /*  set to 1 if next instruction          int             nullify_next;           /*  set to 1 if next instruction
250                                                          is to be nullified  */                                                          is to be nullified  */
251    
         /*  This is set to non-zero, if it is possible at all that an  
             interrupt will occur.  */  
         int             cached_interrupt_is_possible;  
   
252          int             show_trace_delay;       /*  0=normal, > 0 = delay until show_trace  */          int             show_trace_delay;       /*  0=normal, > 0 = delay until show_trace  */
253          uint64_t        show_trace_addr;          uint64_t        show_trace_addr;
254    
255          int             last_was_jumptoself;          int             last_was_jumptoself;
256          int             jump_to_self_reg;          int             jump_to_self_reg;
257    
 #ifdef MFHILO_DELAY  
         int             mfhi_delay;     /*  instructions since last mfhi  */  
         int             mflo_delay;     /*  instructions since last mflo  */  
 #endif  
   
258          int             rmw;            /*  Read-Modify-Write  */          int             rmw;            /*  Read-Modify-Write  */
259          int             rmw_len;        /*  Length of rmw modification  */          int             rmw_len;        /*  Length of rmw modification  */
260          uint64_t        rmw_addr;       /*  Address of rmw modification  */          uint64_t        rmw_addr;       /*  Address of rmw modification  */
261    
262          /*          /*
263           *  TODO:  The R5900 has 128-bit registers. I'm not really sure           *  NOTE:  The R5900 has 128-bit registers. I'm not really sure
264           *  whether they are used a lot or not, at least with code produced           *  whether they are used a lot or not, at least with code produced
265           *  with gcc they are not. An important case however is lq and sq           *  with gcc they are not. An important case however is lq and sq
266           *  (load and store of 128-bit values). These "upper halves" of R5900           *  (load and store of 128-bit values). These "upper halves" of R5900
267           *  quadwords can be used in those cases.           *  quadwords can be used in those cases.
268           *           *
269             *  hi1 and lo1 are the high 64-bit parts of the hi and lo registers.
270             *  sa is a 32-bit "shift amount" register.
271             *
272           *  TODO:  Generalize this.           *  TODO:  Generalize this.
273           */           */
274          uint64_t        gpr_quadhi[N_MIPS_GPRS];          uint64_t        gpr_quadhi[N_MIPS_GPRS];
275            uint64_t        hi1;
276            uint64_t        lo1;
277            uint32_t        r5900_sa;
278    
279    
         /*  
          *  Statistics:  
          */  
         long            stats_opcode[N_HI6];  
         long            stats__special[N_SPECIAL];  
         long            stats__regimm[N_REGIMM];  
         long            stats__special2[N_SPECIAL];  
   
280          /*  Data and Instruction caches:  */          /*  Data and Instruction caches:  */
281          unsigned char   *cache[2];          unsigned char   *cache[2];
282          void            *cache_tags[2];          void            *cache_tags[2];
# Line 437  struct mips_cpu { Line 305  struct mips_cpu {
305    
306    
307  /*  cpu_mips.c:  */  /*  cpu_mips.c:  */
308  void mips_cpu_show_full_statistics(struct machine *m);  int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
309  void mips_cpu_tlbdump(struct machine *m, int x, int rawflag);  void mips_cpu_tlbdump(struct machine *m, int x, int rawflag);
310  void mips_cpu_register_match(struct machine *m, char *name,  void mips_cpu_register_match(struct machine *m, char *name,
311          int writeflag, uint64_t *valuep, int *match_register);          int writeflag, uint64_t *valuep, int *match_register);
312  void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs);  void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs);
313  int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,  int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
314          int running, uint64_t addr, int bintrans);          int running, uint64_t addr);
315  int mips_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr);  int mips_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr);
316  int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr);  int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr);
317  void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr,  void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr,
318          /*  uint64_t pagemask,  */  int coproc_nr, uint64_t vaddr_vpn2,          /*  uint64_t pagemask,  */  int coproc_nr, uint64_t vaddr_vpn2,
319          int vaddr_asid, int x_64);          int vaddr_asid, int x_64);
 void mips_cpu_cause_simple_exception(struct cpu *cpu, int exc_code);  
320  int mips_cpu_run(struct emul *emul, struct machine *machine);  int mips_cpu_run(struct emul *emul, struct machine *machine);
321  void mips_cpu_dumpinfo(struct cpu *cpu);  void mips_cpu_dumpinfo(struct cpu *cpu);
322  void mips_cpu_list_available_types(void);  void mips_cpu_list_available_types(void);
# Line 462  void mips_coproc_tlb_set_entry(struct cp Line 329  void mips_coproc_tlb_set_entry(struct cp
329          uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,          uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,
330          int valid0, int valid1, int dirty0, int dirty1, int global, int asid,          int valid0, int valid1, int dirty0, int dirty1, int global, int asid,
331          int cachealgo0, int cachealgo1);          int cachealgo0, int cachealgo1);
 void mips_OLD_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  
         unsigned char *host_page, int writeflag, uint64_t paddr_page);  
 void clear_all_chunks_from_all_tables(struct cpu *cpu);  
 void mips_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int);  
332  void coproc_register_read(struct cpu *cpu,  void coproc_register_read(struct cpu *cpu,
333          struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select);          struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select);
334  void coproc_register_write(struct cpu *cpu,  void coproc_register_write(struct cpu *cpu,
# Line 486  int mips_memory_rw(struct cpu *cpu, stru Line 349  int mips_memory_rw(struct cpu *cpu, stru
349          unsigned char *data, size_t len, int writeflag, int cache_flags);          unsigned char *data, size_t len, int writeflag, int cache_flags);
350    
351    
352  /*  mips16.c:  */  /*  Dyntrans unaligned load/store:  */
353  int mips16_to_32(struct cpu *cpu, unsigned char *instr16, unsigned char *instr);  void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic,
354            int is_left, int wlen, int store);
355    
356    
 /*  NEW DYNTRANS:  */  
357  void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
358          unsigned char *host_page, int writeflag, uint64_t paddr_page);          unsigned char *host_page, int writeflag, uint64_t paddr_page);
359  void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);  void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
360  void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int);  void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
361    void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
362            unsigned char *host_page, int writeflag, uint64_t paddr_page);
363    void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
364    void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
365    void mips_init_64bit_dummy_tables(struct cpu *cpu);
366    
367    
368  #endif  /*  CPU_MIPS_H  */  #endif  /*  CPU_MIPS_H  */
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