/[gxemul]/trunk/src/include/cpu_mips.h
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revision 14 by dpavlin, Mon Oct 8 16:18:51 2007 UTC revision 28 by dpavlin, Mon Oct 8 16:20:26 2007 UTC
# Line 2  Line 2 
2  #define CPU_MIPS_H  #define CPU_MIPS_H
3    
4  /*  /*
5   *  Copyright (C) 2003-2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2003-2006  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_mips.h,v 1.21 2005/08/28 20:16:24 debug Exp $   *  $Id: cpu_mips.h,v 1.45 2006/07/16 13:32:27 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
35    
 /*    
  *  ENABLE_MIPS16 should be defined on the cc commandline using -D, if you  
  *  want it. (This is done by ./configure --mips16)  
  */  
 /*  #define MFHILO_DELAY  */  
   
36  struct cpu_family;  struct cpu_family;
37  struct emul;  struct emul;
38  struct machine;  struct machine;
# Line 55  struct mips_cpu_type_def { Line 49  struct mips_cpu_type_def {
49          char            exc_model;              /*  EXC3K or EXC4K  */          char            exc_model;              /*  EXC3K or EXC4K  */
50          char            mmu_model;              /*  MMU3K or MMU4K  */          char            mmu_model;              /*  MMU3K or MMU4K  */
51          char            isa_level;              /*  1, 2, 3, 4, 5, 32, 64  */          char            isa_level;              /*  1, 2, 3, 4, 5, 32, 64  */
52            char            isa_revision;           /*  1 or 2 (for MIPS32/64)  */
53          int             nr_of_tlb_entries;      /*  32, 48, 64, ...  */          int             nr_of_tlb_entries;      /*  32, 48, 64, ...  */
54          char            instrs_per_cycle;       /*  simplified, 1, 2, or 4  */          char            instrs_per_cycle;       /*  simplified, 1, 2, or 4  */
55          int             picache;          int             picache;
# Line 74  struct mips_cpu_type_def { Line 69  struct mips_cpu_type_def {
69    
70  /*  /*
71   *  Coproc 0:   *  Coproc 0:
72     *
73     *  NOTE:
74     *      On R3000, only hi and lo0 are used, and then only the lowest 32 bits.
75   */   */
76  #define N_MIPS_COPROC_REGS      32  #define N_MIPS_COPROC_REGS      32
77  struct mips_tlb {  struct mips_tlb {
# Line 87  struct mips_tlb { Line 85  struct mips_tlb {
85  /*  /*
86   *  Coproc 1:   *  Coproc 1:
87   */   */
88  #define N_MIPS_FCRS             32  /*  FPU control registers:  */
89    #define N_MIPS_FCRS                     32
90    #define MIPS_FPU_FCIR                   0
91    #define MIPS_FPU_FCCR                   25
92    #define MIPS_FPU_FCSR                   31
93    #define    MIPS_FCSR_FCC0_SHIFT            23
94    #define    MIPS_FCSR_FCC1_SHIFT            25
95    
96  struct mips_coproc {  struct mips_coproc {
97          int             coproc_nr;          int             coproc_nr;
# Line 156  struct mips_coproc { Line 160  struct mips_coproc {
160  #define MIPS_GPR_FP             30              /*  fp  */  #define MIPS_GPR_FP             30              /*  fp  */
161  #define MIPS_GPR_RA             31              /*  ra  */  #define MIPS_GPR_RA             31              /*  ra  */
162    
 /*  Meaning of delay_slot:  */  
 #define NOT_DELAYED             0  
 #define DELAYED                 1  
 #define TO_BE_DELAYED           2  
   
163  #define N_HI6                   64  #define N_HI6                   64
164  #define N_SPECIAL               64  #define N_SPECIAL               64
165  #define N_REGIMM                32  #define N_REGIMM                32
166    
167  /*  Number of "tiny" translation cache entries:  */  /*******************************  OLD:  *****************************/
 #define N_TRANSLATION_CACHE_INSTR       5  
 #define N_TRANSLATION_CACHE_DATA        5  
   
 struct translation_cache_entry {  
         int             wf;  
         uint64_t        vaddr_pfn;  
         uint64_t        paddr;  
 };  
   
 /*  This should be a value which the program counter  
     can "never" have:  */  
 #define PC_LAST_PAGE_IMPOSSIBLE_VALUE   3  
168    
169  /*  An "impossible" paddr:  */  /*  An "impossible" paddr:  */
170  #define IMPOSSIBLE_PADDR                0x1212343456566767ULL  #define IMPOSSIBLE_PADDR                0x1212343456566767ULL
# Line 196  struct r4000_cache_line { Line 183  struct r4000_cache_line {
183          char            dummy;          char            dummy;
184  };  };
185    
186  #define BINTRANS_DONT_RUN_NEXT          0x1000000  /********************************************************************/
 #define BINTRANS_N_MASK                 0x0ffffff  
187    
188  #define N_SAFE_BINTRANS_LIMIT_SHIFT     14  #ifdef ONEKPAGE
189  #define N_SAFE_BINTRANS_LIMIT   ((1 << (N_SAFE_BINTRANS_LIMIT_SHIFT - 1)) - 1)  #define MIPS_IC_ENTRIES_SHIFT           8
190    #else
191    #define MIPS_IC_ENTRIES_SHIFT           10
192    #endif
193    
194  #define N_BINTRANS_VADDR_TO_HOST        20  #define MIPS_N_IC_ARGS                  3
195    #define MIPS_INSTR_ALIGNMENT_SHIFT      2
196    #define MIPS_IC_ENTRIES_PER_PAGE        (1 << MIPS_IC_ENTRIES_SHIFT)
197    #define MIPS_PC_TO_IC_ENTRY(a)          (((a)>>MIPS_INSTR_ALIGNMENT_SHIFT) \
198                                            & (MIPS_IC_ENTRIES_PER_PAGE-1))
199    #define MIPS_ADDR_TO_PAGENR(a)          ((a) >> (MIPS_IC_ENTRIES_SHIFT \
200                                            + MIPS_INSTR_ALIGNMENT_SHIFT))
201    
202    #define MIPS_L2N                17
203    #define MIPS_L3N                18
204    
205    #define MIPS_MAX_VPH_TLB_ENTRIES        128
206    DYNTRANS_MISC_DECLARATIONS(mips,MIPS,uint64_t)
207    DYNTRANS_MISC64_DECLARATIONS(mips,MIPS,uint8_t)
208    
209    #if 0
210    struct mips_instr_call {
211            void    (*f)(struct cpu *, struct mips_instr_call *);
212            size_t  arg[MIPS_N_IC_ARGS];
213    };
214    
215  /*  Virtual to host address translation tables:  */  /*  Translation cache struct for each physical page:  */
216  struct vth32_table {  struct mips_tc_physpage {
217          void                    *haddr_entry[1024 * 2];          struct mips_instr_call ics[MIPS_IC_ENTRIES_PER_PAGE + 3];
218          uint32_t                paddr_entry[1024];          uint32_t        next_ofs;       /*  or 0 for end of chain  */
219          uint32_t                *bintrans_chunks[1024];          int             flags;
220          struct vth32_table      *next_free;          uint64_t        physaddr;
         int                     refcount;  
221  };  };
222    
223    struct mips_vpg_tlb_entry {
224            uint8_t         valid;
225            uint8_t         writeflag;
226            unsigned char   *host_page;
227            int64_t         timestamp;
228            uint64_t        vaddr_page;
229            uint64_t        paddr_page;
230    };
231    #endif
232    
233    /********************************************************************/
234    
235  struct mips_cpu {  struct mips_cpu {
236          struct mips_cpu_type_def cpu_type;          struct mips_cpu_type_def cpu_type;
237    
# Line 221  struct mips_cpu { Line 240  struct mips_cpu {
240          int             compare_register_set;          int             compare_register_set;
241    
242          /*  Special purpose registers:  */          /*  Special purpose registers:  */
         uint64_t        pc_last;                /*  PC of last instruction   */  
243          uint64_t        hi;          uint64_t        hi;
244          uint64_t        lo;          uint64_t        lo;
245    
246            /*  Dummy destination register when writing to the zero register:  */
247            uint64_t        scratch;
248    
249          /*  General purpose registers:  */          /*  General purpose registers:  */
250          uint64_t        gpr[N_MIPS_GPRS];          uint64_t        gpr[N_MIPS_GPRS];
251    
         /*  
          *  The translation_cached stuff is used to speed up the  
          *  most recent lookups into the TLB.  Whenever the TLB is  
          *  written to, translation_cached[] must be filled with zeros.  
          */  
 #ifdef USE_TINY_CACHE  
         struct translation_cache_entry  
                         translation_cache_instr[N_TRANSLATION_CACHE_INSTR];  
         struct translation_cache_entry  
                         translation_cache_data[N_TRANSLATION_CACHE_DATA];  
 #endif  
   
         /*  
          *  For faster memory lookup when running instructions:  
          *  
          *  Reading memory to load instructions is a very common thing in the  
          *  emulator, and an instruction is very often read from the address  
          *  following the previously executed instruction. That means that we  
          *  don't have to go through the TLB each time.  
          *  
          *  We then get the vaddr -> paddr translation for free. There is an  
          *  even better case when the paddr is a RAM address (as opposed to an  
          *  address in a memory mapped device). Then we can figure out the  
          *  address in the host's memory directly, and skip the paddr -> host  
          *  address calculation as well.  
          *  
          *  A modification to the TLB should set the virtual_page variable to  
          *  an "impossible" value, so that there won't be a hit on the next  
          *  instruction.  
          */  
         uint64_t        pc_last_virtual_page;  
         uint64_t        pc_last_physical_page;  
         unsigned char   *pc_last_host_4k_page;  
   
         /*  MIPS Bintrans:  */  
         int             dont_run_next_bintrans;  
         int             bintrans_instructions_executed;  /*  set to the  
                                 number of bintranslated instructions executed  
                                 when running a bintrans codechunk  */  
         int             pc_bintrans_paddr_valid;  
         uint64_t        pc_bintrans_paddr;  
         unsigned char   *pc_bintrans_host_4kpage;  
   
         /*  Chunk base address:  */  
         unsigned char   *chunk_base_address;  
   
         /*  This should work for 32-bit MIPS emulation:  */  
         struct vth32_table *vaddr_to_hostaddr_nulltable;  
         struct vth32_table *vaddr_to_hostaddr_r2k3k_icachetable;  
         struct vth32_table *vaddr_to_hostaddr_r2k3k_dcachetable;  
         struct vth32_table **vaddr_to_hostaddr_table0_kernel;  
         struct vth32_table **vaddr_to_hostaddr_table0_cacheisol_i;  
         struct vth32_table **vaddr_to_hostaddr_table0_cacheisol_d;  
         struct vth32_table **vaddr_to_hostaddr_table0_user;  
         struct vth32_table **vaddr_to_hostaddr_table0;  /*  should point to kernel or user  */  
         struct vth32_table *next_free_vth_table;  
   
 /*  Testing...  */  
         unsigned char   **host_load;  
         unsigned char   **host_store;  
         unsigned char   **host_load_orig;  
         unsigned char   **host_store_orig;  
         unsigned char   **huge_r2k3k_cache_table;  
   
         /*  For 64-bit (generic) emulation:  */  
         unsigned char   *(*fast_vaddr_to_hostaddr)(struct cpu *cpu,  
                             uint64_t vaddr, int writeflag);  
         int             bintrans_next_index;  
         int             bintrans_data_writable[N_BINTRANS_VADDR_TO_HOST];  
         uint64_t        bintrans_data_vaddr[N_BINTRANS_VADDR_TO_HOST];  
         unsigned char   *bintrans_data_hostpage[N_BINTRANS_VADDR_TO_HOST];  
   
         void            (*bintrans_load_32bit)(struct cpu *);   /*  Note: incorrect args  */  
         void            (*bintrans_store_32bit)(struct cpu *);  /*  Note: incorrect args  */  
         void            (*bintrans_jump_to_32bit_pc)(struct cpu *);  
         void            (*bintrans_simple_exception)(struct cpu *, int);  
         void            (*bintrans_fast_rfe)(struct cpu *);  
         void            (*bintrans_fast_eret)(struct cpu *);  
         void            (*bintrans_fast_tlbwri)(struct cpu *, int);  
         void            (*bintrans_fast_tlbpr)(struct cpu *, int);  
   
 #ifdef ENABLE_MIPS16  
         int             mips16;                 /*  non-zero if MIPS16 code is allowed  */  
         uint16_t        mips16_extend;          /*  set on 'extend' instructions to the entire 16-bit extend instruction  */  
 #endif  
   
 #ifdef ENABLE_INSTRUCTION_DELAYS  
         int             instruction_delay;  
 #endif  
   
         uint64_t        delay_jmpaddr;          /*  only used if delay_slot > 0  */  
         int             delay_slot;  
252          int             nullify_next;           /*  set to 1 if next instruction          int             nullify_next;           /*  set to 1 if next instruction
253                                                          is to be nullified  */                                                          is to be nullified  */
254    
         /*  This is set to non-zero, if it is possible at all that an  
             interrupt will occur.  */  
         int             cached_interrupt_is_possible;  
   
255          int             show_trace_delay;       /*  0=normal, > 0 = delay until show_trace  */          int             show_trace_delay;       /*  0=normal, > 0 = delay until show_trace  */
256          uint64_t        show_trace_addr;          uint64_t        show_trace_addr;
257    
258          int             last_was_jumptoself;          int             last_was_jumptoself;
259          int             jump_to_self_reg;          int             jump_to_self_reg;
260    
 #ifdef MFHILO_DELAY  
         int             mfhi_delay;     /*  instructions since last mfhi  */  
         int             mflo_delay;     /*  instructions since last mflo  */  
 #endif  
   
261          int             rmw;            /*  Read-Modify-Write  */          int             rmw;            /*  Read-Modify-Write  */
262          int             rmw_len;        /*  Length of rmw modification  */          int             rmw_len;        /*  Length of rmw modification  */
263          uint64_t        rmw_addr;       /*  Address of rmw modification  */          uint64_t        rmw_addr;       /*  Address of rmw modification  */
264    
265          /*          /*
266           *  TODO:  The R5900 has 128-bit registers. I'm not really sure           *  NOTE:  The R5900 has 128-bit registers. I'm not really sure
267           *  whether they are used a lot or not, at least with code produced           *  whether they are used a lot or not, at least with code produced
268           *  with gcc they are not. An important case however is lq and sq           *  with gcc they are not. An important case however is lq and sq
269           *  (load and store of 128-bit values). These "upper halves" of R5900           *  (load and store of 128-bit values). These "upper halves" of R5900
270           *  quadwords can be used in those cases.           *  quadwords can be used in those cases.
271           *           *
272             *  hi1 and lo1 are the high 64-bit parts of the hi and lo registers.
273             *  sa is a 32-bit "shift amount" register.
274             *
275           *  TODO:  Generalize this.           *  TODO:  Generalize this.
276           */           */
277          uint64_t        gpr_quadhi[N_MIPS_GPRS];          uint64_t        gpr_quadhi[N_MIPS_GPRS];
278            uint64_t        hi1;
279            uint64_t        lo1;
280            uint32_t        r5900_sa;
281    
282    
         /*  
          *  Statistics:  
          */  
         long            stats_opcode[N_HI6];  
         long            stats__special[N_SPECIAL];  
         long            stats__regimm[N_REGIMM];  
         long            stats__special2[N_SPECIAL];  
   
283          /*  Data and Instruction caches:  */          /*  Data and Instruction caches:  */
284          unsigned char   *cache[2];          unsigned char   *cache[2];
285          void            *cache_tags[2];          void            *cache_tags[2];
# Line 373  struct mips_cpu { Line 291  struct mips_cpu {
291    
292          /*  Other stuff:  */          /*  Other stuff:  */
293          uint64_t        cop0_config_select1;          uint64_t        cop0_config_select1;
294    
295    
296            /*  NEW DYNTRANS:  */
297    
298    
299            /*
300             *  Instruction translation cache and Virtual->Physical->Host
301             *  address translation:
302             */
303            DYNTRANS_ITC(mips)
304            VPH_TLBS(mips,MIPS)
305            VPH32(mips,MIPS,uint64_t,uint8_t)
306            VPH64(mips,MIPS,uint8_t)
307  };  };
308    
309    
310  /*  cpu_mips.c:  */  /*  cpu_mips.c:  */
311  void mips_cpu_show_full_statistics(struct machine *m);  int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
312  void mips_cpu_tlbdump(struct machine *m, int x, int rawflag);  void mips_cpu_tlbdump(struct machine *m, int x, int rawflag);
313  void mips_cpu_register_match(struct machine *m, char *name,  void mips_cpu_register_match(struct machine *m, char *name,
314          int writeflag, uint64_t *valuep, int *match_register);          int writeflag, uint64_t *valuep, int *match_register);
315  void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs);  void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs);
316  int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,  int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
317          int running, uint64_t addr, int bintrans);          int running, uint64_t addr);
318  int mips_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr);  int mips_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr);
319  int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr);  int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr);
320  void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr,  void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr,
321          /*  uint64_t pagemask,  */  int coproc_nr, uint64_t vaddr_vpn2,          /*  uint64_t pagemask,  */  int coproc_nr, uint64_t vaddr_vpn2,
322          int vaddr_asid, int x_64);          int vaddr_asid, int x_64);
 void mips_cpu_cause_simple_exception(struct cpu *cpu, int exc_code);  
323  int mips_cpu_run(struct emul *emul, struct machine *machine);  int mips_cpu_run(struct emul *emul, struct machine *machine);
324  void mips_cpu_dumpinfo(struct cpu *cpu);  void mips_cpu_dumpinfo(struct cpu *cpu);
325  void mips_cpu_list_available_types(void);  void mips_cpu_list_available_types(void);
# Line 402  void mips_coproc_tlb_set_entry(struct cp Line 332  void mips_coproc_tlb_set_entry(struct cp
332          uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,          uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,
333          int valid0, int valid1, int dirty0, int dirty1, int global, int asid,          int valid0, int valid1, int dirty0, int dirty1, int global, int asid,
334          int cachealgo0, int cachealgo1);          int cachealgo0, int cachealgo1);
 void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  
         unsigned char *host_page, int writeflag, uint64_t paddr_page);  
 void clear_all_chunks_from_all_tables(struct cpu *cpu);  
 void mips_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int);  
335  void coproc_register_read(struct cpu *cpu,  void coproc_register_read(struct cpu *cpu,
336          struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select);          struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select);
337  void coproc_register_write(struct cpu *cpu,  void coproc_register_write(struct cpu *cpu,
# Line 425  int memory_cache_R3000(struct cpu *cpu, Line 351  int memory_cache_R3000(struct cpu *cpu,
351  int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,  int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
352          unsigned char *data, size_t len, int writeflag, int cache_flags);          unsigned char *data, size_t len, int writeflag, int cache_flags);
353    
354    int translate_v2p_mmu3k(struct cpu *cpu, uint64_t vaddr,
355            uint64_t *return_addr, int flags);
356    int translate_v2p_mmu8k(struct cpu *cpu, uint64_t vaddr,
357            uint64_t *return_addr, int flags);
358    int translate_v2p_mmu10k(struct cpu *cpu, uint64_t vaddr,
359            uint64_t *return_addr, int flags);
360    int translate_v2p_mmu4100(struct cpu *cpu, uint64_t vaddr,
361            uint64_t *return_addr, int flags);
362    int translate_v2p_generic(struct cpu *cpu, uint64_t vaddr,
363            uint64_t *return_addr, int flags);
364    
365    
366    /*  Dyntrans unaligned load/store:  */
367    void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic,
368            int is_left, int wlen, int store);
369    
370  /*  mips16.c:  */  
371  int mips16_to_32(struct cpu *cpu, unsigned char *instr16, unsigned char *instr);  int mips_run_instr(struct cpu *cpu);
372    void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
373            unsigned char *host_page, int writeflag, uint64_t paddr_page);
374    void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
375    void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
376    int mips32_run_instr(struct cpu *cpu);
377    void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
378            unsigned char *host_page, int writeflag, uint64_t paddr_page);
379    void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
380    void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
381    
382    
383  #endif  /*  CPU_MIPS_H  */  #endif  /*  CPU_MIPS_H  */
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