/[gxemul]/trunk/src/include/cpu_mips.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 14 by dpavlin, Mon Oct 8 16:18:51 2007 UTC revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC
# Line 2  Line 2 
2  #define CPU_MIPS_H  #define CPU_MIPS_H
3    
4  /*  /*
5   *  Copyright (C) 2003-2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2003-2006  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_mips.h,v 1.21 2005/08/28 20:16:24 debug Exp $   *  $Id: cpu_mips.h,v 1.26 2006/02/13 04:23:25 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
# Line 157  struct mips_coproc { Line 157  struct mips_coproc {
157  #define MIPS_GPR_RA             31              /*  ra  */  #define MIPS_GPR_RA             31              /*  ra  */
158    
159  /*  Meaning of delay_slot:  */  /*  Meaning of delay_slot:  */
160  #define NOT_DELAYED             0  #define NOT_DELAYED                     0
161  #define DELAYED                 1  #define DELAYED                         1
162  #define TO_BE_DELAYED           2  #define TO_BE_DELAYED                   2
163    #define EXCEPTION_IN_DELAY_SLOT         0x100
164    
165  #define N_HI6                   64  #define N_HI6                   64
166  #define N_SPECIAL               64  #define N_SPECIAL               64
167  #define N_REGIMM                32  #define N_REGIMM                32
168    
169    /*******************************  OLD:  *****************************/
170    
171  /*  Number of "tiny" translation cache entries:  */  /*  Number of "tiny" translation cache entries:  */
172  #define N_TRANSLATION_CACHE_INSTR       5  #define N_TRANSLATION_CACHE_INSTR       5
173  #define N_TRANSLATION_CACHE_DATA        5  #define N_TRANSLATION_CACHE_DATA        5
# Line 196  struct r4000_cache_line { Line 199  struct r4000_cache_line {
199          char            dummy;          char            dummy;
200  };  };
201    
202    /********************************************************************/
203    
204    #ifdef ONEKPAGE
205    #define MIPS_IC_ENTRIES_SHIFT           8
206    #else
207    #define MIPS_IC_ENTRIES_SHIFT           10
208    #endif
209    
210    #define MIPS_N_IC_ARGS                  3
211    #define MIPS_INSTR_ALIGNMENT_SHIFT      2
212    #define MIPS_IC_ENTRIES_PER_PAGE        (1 << MIPS_IC_ENTRIES_SHIFT)
213    #define MIPS_PC_TO_IC_ENTRY(a)          (((a)>>MIPS_INSTR_ALIGNMENT_SHIFT) \
214                                            & (MIPS_IC_ENTRIES_PER_PAGE-1))
215    #define MIPS_ADDR_TO_PAGENR(a)          ((a) >> (MIPS_IC_ENTRIES_SHIFT \
216                                            + MIPS_INSTR_ALIGNMENT_SHIFT))
217    
218    struct mips_instr_call {
219            void    (*f)(struct cpu *, struct mips_instr_call *);
220            size_t  arg[MIPS_N_IC_ARGS];
221    };
222    
223    /*  Translation cache struct for each physical page:  */
224    struct mips_tc_physpage {
225            struct mips_instr_call ics[MIPS_IC_ENTRIES_PER_PAGE + 3];
226            uint32_t        next_ofs;       /*  or 0 for end of chain  */
227            int             flags;
228            uint64_t        physaddr;
229    };
230    
231    #define MIPS_MAX_VPH_TLB_ENTRIES        128
232    struct mips_vpg_tlb_entry {
233            uint8_t         valid;
234            uint8_t         writeflag;
235            unsigned char   *host_page;
236            int64_t         timestamp;
237            uint64_t        vaddr_page;
238            uint64_t        paddr_page;
239    };
240    
241    
242    /*******************************  OLD:  *****************************/
243    
244  #define BINTRANS_DONT_RUN_NEXT          0x1000000  #define BINTRANS_DONT_RUN_NEXT          0x1000000
245  #define BINTRANS_N_MASK                 0x0ffffff  #define BINTRANS_N_MASK                 0x0ffffff
246    
# Line 213  struct vth32_table { Line 258  struct vth32_table {
258          int                     refcount;          int                     refcount;
259  };  };
260    
261    /********************************************************************/
262    
263  struct mips_cpu {  struct mips_cpu {
264          struct mips_cpu_type_def cpu_type;          struct mips_cpu_type_def cpu_type;
265    
# Line 286  struct mips_cpu { Line 333  struct mips_cpu {
333          struct vth32_table *next_free_vth_table;          struct vth32_table *next_free_vth_table;
334    
335  /*  Testing...  */  /*  Testing...  */
336          unsigned char   **host_load;          unsigned char   **host_OLD_load;
337          unsigned char   **host_store;          unsigned char   **host_OLD_store;
338          unsigned char   **host_load_orig;          unsigned char   **host_load_orig;
339          unsigned char   **host_store_orig;          unsigned char   **host_store_orig;
340          unsigned char   **huge_r2k3k_cache_table;          unsigned char   **huge_r2k3k_cache_table;
# Line 373  struct mips_cpu { Line 420  struct mips_cpu {
420    
421          /*  Other stuff:  */          /*  Other stuff:  */
422          uint64_t        cop0_config_select1;          uint64_t        cop0_config_select1;
423    
424    
425            /*  NEW DYNTRANS:  */
426    
427    
428            /*
429             *  Instruction translation cache and Virtual->Physical->Host
430             *  address translation:
431             */
432            DYNTRANS_ITC(mips)
433            VPH_TLBS(mips,MIPS)
434            VPH32(mips,MIPS,uint64_t,uint8_t)
435            VPH64(mips,MIPS,uint8_t)
436  };  };
437    
438    
# Line 402  void mips_coproc_tlb_set_entry(struct cp Line 462  void mips_coproc_tlb_set_entry(struct cp
462          uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,          uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,
463          int valid0, int valid1, int dirty0, int dirty1, int global, int asid,          int valid0, int valid1, int dirty0, int dirty1, int global, int asid,
464          int cachealgo0, int cachealgo1);          int cachealgo0, int cachealgo1);
465  void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void mips_OLD_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
466          unsigned char *host_page, int writeflag, uint64_t paddr_page);          unsigned char *host_page, int writeflag, uint64_t paddr_page);
467  void clear_all_chunks_from_all_tables(struct cpu *cpu);  void clear_all_chunks_from_all_tables(struct cpu *cpu);
468  void mips_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int);  void mips_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int);
# Line 430  int mips_memory_rw(struct cpu *cpu, stru Line 490  int mips_memory_rw(struct cpu *cpu, stru
490  int mips16_to_32(struct cpu *cpu, unsigned char *instr16, unsigned char *instr);  int mips16_to_32(struct cpu *cpu, unsigned char *instr16, unsigned char *instr);
491    
492    
493    /*  NEW DYNTRANS:  */
494    void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
495            unsigned char *host_page, int writeflag, uint64_t paddr_page);
496    void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
497    void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
498    
499    
500  #endif  /*  CPU_MIPS_H  */  #endif  /*  CPU_MIPS_H  */
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