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#define CPU_MIPS_H |
#define CPU_MIPS_H |
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/* |
/* |
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* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_mips.h,v 1.42 2006/06/22 13:22:41 debug Exp $ |
* $Id: cpu_mips.h,v 1.56 2007/04/28 09:19:52 debug Exp $ |
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*/ |
*/ |
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#include "interrupt.h" |
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#include "misc.h" |
#include "misc.h" |
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struct cpu_family; |
struct cpu_family; |
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struct emul; |
struct emul; |
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struct machine; |
struct machine; |
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struct timer; |
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/* |
/* |
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* CPU type definitions: See mips_cpu_types.h. |
* CPU type definitions: See mips_cpu_types.h. |
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/* |
/* |
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* Coproc 0: |
* Coproc 0: |
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* |
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* NOTE: |
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* On R3000, only hi and lo0 are used, and then only the lowest 32 bits. |
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*/ |
*/ |
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#define N_MIPS_COPROC_REGS 32 |
#define N_MIPS_COPROC_REGS 32 |
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struct mips_tlb { |
struct mips_tlb { |
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#define MIPS_FCSR_FCC0_SHIFT 23 |
#define MIPS_FCSR_FCC0_SHIFT 23 |
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#define MIPS_FCSR_FCC1_SHIFT 25 |
#define MIPS_FCSR_FCC1_SHIFT 25 |
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#define N_VADDR_TO_TLB_INDEX_ENTRIES (1 << 20) |
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struct mips_coproc { |
struct mips_coproc { |
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int coproc_nr; |
int coproc_nr; |
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uint64_t reg[N_MIPS_COPROC_REGS]; |
uint64_t reg[N_MIPS_COPROC_REGS]; |
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#define N_SPECIAL 64 |
#define N_SPECIAL 64 |
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#define N_REGIMM 32 |
#define N_REGIMM 32 |
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/******************************* OLD: *****************************/ |
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/* An "impossible" paddr: */ |
/* An "impossible" paddr: */ |
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#define IMPOSSIBLE_PADDR 0x1212343456566767ULL |
#define IMPOSSIBLE_PADDR 0x1212343456566767ULL |
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char dummy; |
char dummy; |
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}; |
}; |
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/********************************************************************/ |
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#ifdef ONEKPAGE |
#ifdef ONEKPAGE |
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#define MIPS_IC_ENTRIES_SHIFT 8 |
#define MIPS_IC_ENTRIES_SHIFT 8 |
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DYNTRANS_MISC_DECLARATIONS(mips,MIPS,uint64_t) |
DYNTRANS_MISC_DECLARATIONS(mips,MIPS,uint64_t) |
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DYNTRANS_MISC64_DECLARATIONS(mips,MIPS,uint8_t) |
DYNTRANS_MISC64_DECLARATIONS(mips,MIPS,uint8_t) |
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#if 0 |
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struct mips_instr_call { |
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void (*f)(struct cpu *, struct mips_instr_call *); |
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size_t arg[MIPS_N_IC_ARGS]; |
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}; |
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/* Translation cache struct for each physical page: */ |
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struct mips_tc_physpage { |
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struct mips_instr_call ics[MIPS_IC_ENTRIES_PER_PAGE + 3]; |
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uint32_t next_ofs; /* or 0 for end of chain */ |
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int flags; |
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uint64_t physaddr; |
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}; |
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struct mips_vpg_tlb_entry { |
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uint8_t valid; |
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uint8_t writeflag; |
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unsigned char *host_page; |
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int64_t timestamp; |
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uint64_t vaddr_page; |
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uint64_t paddr_page; |
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}; |
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#endif |
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/********************************************************************/ |
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struct mips_cpu { |
struct mips_cpu { |
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struct mips_cpu_type_def cpu_type; |
struct mips_cpu_type_def cpu_type; |
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struct mips_coproc *coproc[N_MIPS_COPROCS]; |
/* General purpose registers: */ |
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uint64_t gpr[N_MIPS_GPRS]; |
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int compare_register_set; |
/* Dummy destination register when writing to the zero register: */ |
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uint64_t scratch; |
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/* Special purpose registers: */ |
/* Special purpose registers: */ |
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uint64_t hi; |
uint64_t hi; |
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uint64_t lo; |
uint64_t lo; |
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/* Dummy destination register when writing to the zero register: */ |
/* Coprocessors: */ |
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uint64_t scratch; |
struct mips_coproc *coproc[N_MIPS_COPROCS]; |
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uint64_t cop0_config_select1; |
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/* General purpose registers: */ |
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uint64_t gpr[N_MIPS_GPRS]; |
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int nullify_next; /* set to 1 if next instruction |
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is to be nullified */ |
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int show_trace_delay; /* 0=normal, > 0 = delay until show_trace */ |
int last_written_tlb_index; |
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uint64_t show_trace_addr; |
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int last_was_jumptoself; |
/* Count/compare timer: */ |
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int jump_to_self_reg; |
int compare_register_set; |
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int compare_interrupts_pending; |
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struct interrupt irq_compare; |
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struct timer *timer; |
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int rmw; /* Read-Modify-Write */ |
int rmw; /* Read-Modify-Write */ |
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int rmw_len; /* Length of rmw modification */ |
uint64_t rmw_len; /* Length of rmw modification */ |
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uint64_t rmw_addr; /* Address of rmw modification */ |
uint64_t rmw_addr; /* Address of rmw modification */ |
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/* |
/* |
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uint64_t lo1; |
uint64_t lo1; |
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uint32_t r5900_sa; |
uint32_t r5900_sa; |
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/* Data and Instruction caches: */ |
/* Data and Instruction caches: */ |
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unsigned char *cache[2]; |
unsigned char *cache[2]; |
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void *cache_tags[2]; |
void *cache_tags[2]; |
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int cache_mask[2]; |
int cache_mask[2]; |
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int cache_miss_penalty[2]; |
int cache_miss_penalty[2]; |
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/* Other stuff: */ |
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uint64_t cop0_config_select1; |
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/* NEW DYNTRANS: */ |
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/* |
/* |
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* Instruction translation cache and Virtual->Physical->Host |
* Instruction translation cache and Virtual->Physical->Host |
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/* cpu_mips.c: */ |
/* cpu_mips.c: */ |
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void mips_cpu_interrupt_assert(struct interrupt *interrupt); |
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void mips_cpu_interrupt_deassert(struct interrupt *interrupt); |
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int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib); |
int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib); |
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void mips_cpu_tlbdump(struct machine *m, int x, int rawflag); |
void mips_cpu_tlbdump(struct machine *m, int x, int rawflag); |
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void mips_cpu_register_match(struct machine *m, char *name, |
void mips_cpu_register_match(struct machine *m, char *name, |
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void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs); |
void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs); |
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int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
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int running, uint64_t addr); |
int running, uint64_t addr); |
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int mips_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr); |
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int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr); |
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void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr, |
void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr, |
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/* uint64_t pagemask, */ int coproc_nr, uint64_t vaddr_vpn2, |
/* uint64_t pagemask, */ int coproc_nr, uint64_t vaddr_vpn2, |
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int vaddr_asid, int x_64); |
int vaddr_asid, int x_64); |
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int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, int writeflag, int cache_flags); |
unsigned char *data, size_t len, int writeflag, int cache_flags); |
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int translate_v2p_mmu3k(struct cpu *cpu, uint64_t vaddr, |
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uint64_t *return_addr, int flags); |
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int translate_v2p_mmu8k(struct cpu *cpu, uint64_t vaddr, |
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uint64_t *return_addr, int flags); |
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int translate_v2p_mmu10k(struct cpu *cpu, uint64_t vaddr, |
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uint64_t *return_addr, int flags); |
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int translate_v2p_mmu4100(struct cpu *cpu, uint64_t vaddr, |
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uint64_t *return_addr, int flags); |
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int translate_v2p_generic(struct cpu *cpu, uint64_t vaddr, |
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uint64_t *return_addr, int flags); |
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/* Dyntrans unaligned load/store: */ |
/* Dyntrans unaligned load/store: */ |
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void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic, |
void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic, |
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int is_left, int wlen, int store); |
int is_left, int wlen, int store); |
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int mips_run_instr(struct cpu *cpu); |
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void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
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void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
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int mips32_run_instr(struct cpu *cpu); |
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void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
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void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
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void mips_init_64bit_dummy_tables(struct cpu *cpu); |
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#endif /* CPU_MIPS_H */ |
#endif /* CPU_MIPS_H */ |