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#define CPU_MIPS_H |
#define CPU_MIPS_H |
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/* |
/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_mips.h,v 1.13 2005/03/14 12:49:16 debug Exp $ |
* $Id: cpu_mips.h,v 1.43 2006/06/24 21:47:24 debug Exp $ |
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*/ |
*/ |
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#include "misc.h" |
#include "misc.h" |
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/* |
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* ENABLE_MIPS16 should be defined on the cc commandline using -D, if you |
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* want it. (This is done by ./configure --mips16) |
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*/ |
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/* #define MFHILO_DELAY */ |
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struct cpu_family; |
struct cpu_family; |
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struct emul; |
struct emul; |
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struct machine; |
struct machine; |
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char exc_model; /* EXC3K or EXC4K */ |
char exc_model; /* EXC3K or EXC4K */ |
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char mmu_model; /* MMU3K or MMU4K */ |
char mmu_model; /* MMU3K or MMU4K */ |
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char isa_level; /* 1, 2, 3, 4, 5, 32, 64 */ |
char isa_level; /* 1, 2, 3, 4, 5, 32, 64 */ |
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char isa_revision; /* 1 or 2 (for MIPS32/64) */ |
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int nr_of_tlb_entries; /* 32, 48, 64, ... */ |
int nr_of_tlb_entries; /* 32, 48, 64, ... */ |
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char instrs_per_cycle; /* simplified, 1, 2, or 4 */ |
char instrs_per_cycle; /* simplified, 1, 2, or 4 */ |
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int default_picache; |
int picache; |
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int default_pdcache; |
int pilinesize; |
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int default_pilinesize; |
int piways; |
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int default_pdlinesize; |
int pdcache; |
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int default_scache; |
int pdlinesize; |
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int default_slinesize; |
int pdways; |
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int scache; |
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int slinesize; |
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int sways; |
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}; |
}; |
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#define INITIAL_PC 0xffffffffbfc00000ULL |
#define INITIAL_PC 0xffffffffbfc00000ULL |
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/* |
/* |
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* Coproc 1: |
* Coproc 1: |
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*/ |
*/ |
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#define N_MIPS_FCRS 32 |
/* FPU control registers: */ |
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#define N_MIPS_FCRS 32 |
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#define MIPS_FPU_FCIR 0 |
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#define MIPS_FPU_FCCR 25 |
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#define MIPS_FPU_FCSR 31 |
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#define MIPS_FCSR_FCC0_SHIFT 23 |
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#define MIPS_FCSR_FCC1_SHIFT 25 |
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struct mips_coproc { |
struct mips_coproc { |
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int coproc_nr; |
int coproc_nr; |
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#define MIPS_GPR_FP 30 /* fp */ |
#define MIPS_GPR_FP 30 /* fp */ |
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#define MIPS_GPR_RA 31 /* ra */ |
#define MIPS_GPR_RA 31 /* ra */ |
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/* Meaning of delay_slot: */ |
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#define NOT_DELAYED 0 |
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#define DELAYED 1 |
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#define TO_BE_DELAYED 2 |
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#define N_HI6 64 |
#define N_HI6 64 |
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#define N_SPECIAL 64 |
#define N_SPECIAL 64 |
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#define N_REGIMM 32 |
#define N_REGIMM 32 |
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/* Number of "tiny" translation cache entries: */ |
/******************************* OLD: *****************************/ |
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#define N_TRANSLATION_CACHE_INSTR 5 |
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#define N_TRANSLATION_CACHE_DATA 5 |
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struct translation_cache_entry { |
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int wf; |
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uint64_t vaddr_pfn; |
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uint64_t paddr; |
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}; |
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/* This should be a value which the program counter |
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can "never" have: */ |
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#define PC_LAST_PAGE_IMPOSSIBLE_VALUE 3 |
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/* An "impossible" paddr: */ |
/* An "impossible" paddr: */ |
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#define IMPOSSIBLE_PADDR 0x1212343456566767ULL |
#define IMPOSSIBLE_PADDR 0x1212343456566767ULL |
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char dummy; |
char dummy; |
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}; |
}; |
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#define BINTRANS_DONT_RUN_NEXT 0x1000000 |
/********************************************************************/ |
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#define BINTRANS_N_MASK 0x0ffffff |
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#define N_SAFE_BINTRANS_LIMIT_SHIFT 14 |
#ifdef ONEKPAGE |
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#define N_SAFE_BINTRANS_LIMIT ((1 << (N_SAFE_BINTRANS_LIMIT_SHIFT - 1)) - 1) |
#define MIPS_IC_ENTRIES_SHIFT 8 |
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#else |
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#define MIPS_IC_ENTRIES_SHIFT 10 |
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#endif |
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#define N_BINTRANS_VADDR_TO_HOST 20 |
#define MIPS_N_IC_ARGS 3 |
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#define MIPS_INSTR_ALIGNMENT_SHIFT 2 |
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#define MIPS_IC_ENTRIES_PER_PAGE (1 << MIPS_IC_ENTRIES_SHIFT) |
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#define MIPS_PC_TO_IC_ENTRY(a) (((a)>>MIPS_INSTR_ALIGNMENT_SHIFT) \ |
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& (MIPS_IC_ENTRIES_PER_PAGE-1)) |
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#define MIPS_ADDR_TO_PAGENR(a) ((a) >> (MIPS_IC_ENTRIES_SHIFT \ |
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+ MIPS_INSTR_ALIGNMENT_SHIFT)) |
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#define MIPS_L2N 17 |
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#define MIPS_L3N 18 |
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#define MIPS_MAX_VPH_TLB_ENTRIES 128 |
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DYNTRANS_MISC_DECLARATIONS(mips,MIPS,uint64_t) |
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DYNTRANS_MISC64_DECLARATIONS(mips,MIPS,uint8_t) |
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#if 0 |
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struct mips_instr_call { |
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void (*f)(struct cpu *, struct mips_instr_call *); |
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size_t arg[MIPS_N_IC_ARGS]; |
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}; |
211 |
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/* Translation cache struct for each physical page: */ |
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struct mips_tc_physpage { |
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struct mips_instr_call ics[MIPS_IC_ENTRIES_PER_PAGE + 3]; |
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uint32_t next_ofs; /* or 0 for end of chain */ |
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int flags; |
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uint64_t physaddr; |
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}; |
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/* Virtual to host address translation tables: */ |
struct mips_vpg_tlb_entry { |
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struct vth32_table { |
uint8_t valid; |
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void *haddr_entry[1024]; |
uint8_t writeflag; |
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uint32_t paddr_entry[1024]; |
unsigned char *host_page; |
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uint32_t *bintrans_chunks[1024]; |
int64_t timestamp; |
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struct vth32_table *next_free; |
uint64_t vaddr_page; |
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int refcount; |
uint64_t paddr_page; |
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}; |
}; |
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#endif |
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/********************************************************************/ |
231 |
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struct mips_cpu { |
struct mips_cpu { |
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struct mips_cpu_type_def cpu_type; |
struct mips_cpu_type_def cpu_type; |
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int compare_register_set; |
int compare_register_set; |
238 |
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/* Special purpose registers: */ |
/* Special purpose registers: */ |
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uint64_t pc_last; /* PC of last instruction */ |
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uint64_t hi; |
uint64_t hi; |
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uint64_t lo; |
uint64_t lo; |
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243 |
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/* Dummy destination register when writing to the zero register: */ |
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uint64_t scratch; |
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/* General purpose registers: */ |
/* General purpose registers: */ |
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uint64_t gpr[N_MIPS_GPRS]; |
uint64_t gpr[N_MIPS_GPRS]; |
248 |
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/* |
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* The translation_cached stuff is used to speed up the |
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* most recent lookups into the TLB. Whenever the TLB is |
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* written to, translation_cached[] must be filled with zeros. |
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*/ |
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#ifdef USE_TINY_CACHE |
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struct translation_cache_entry |
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translation_cache_instr[N_TRANSLATION_CACHE_INSTR]; |
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struct translation_cache_entry |
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translation_cache_data[N_TRANSLATION_CACHE_DATA]; |
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#endif |
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/* |
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* For faster memory lookup when running instructions: |
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* |
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* Reading memory to load instructions is a very common thing in the |
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* emulator, and an instruction is very often read from the address |
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* following the previously executed instruction. That means that we |
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* don't have to go through the TLB each time. |
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* |
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* We then get the vaddr -> paddr translation for free. There is an |
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* even better case when the paddr is a RAM address (as opposed to an |
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* address in a memory mapped device). Then we can figure out the |
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* address in the host's memory directly, and skip the paddr -> host |
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* address calculation as well. |
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* |
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* A modification to the TLB should set the virtual_page variable to |
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* an "impossible" value, so that there won't be a hit on the next |
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* instruction. |
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*/ |
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uint64_t pc_last_virtual_page; |
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uint64_t pc_last_physical_page; |
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unsigned char *pc_last_host_4k_page; |
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#ifdef BINTRANS |
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int dont_run_next_bintrans; |
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int bintrans_instructions_executed; /* set to the |
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number of bintranslated instructions executed |
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when running a bintrans codechunk */ |
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int pc_bintrans_paddr_valid; |
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uint64_t pc_bintrans_paddr; |
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unsigned char *pc_bintrans_host_4kpage; |
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/* Chunk base address: */ |
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unsigned char *chunk_base_address; |
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/* This should work for 32-bit MIPS emulation: */ |
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struct vth32_table *vaddr_to_hostaddr_nulltable; |
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struct vth32_table *vaddr_to_hostaddr_r2k3k_icachetable; |
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struct vth32_table *vaddr_to_hostaddr_r2k3k_dcachetable; |
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struct vth32_table **vaddr_to_hostaddr_table0_kernel; |
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struct vth32_table **vaddr_to_hostaddr_table0_cacheisol_i; |
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struct vth32_table **vaddr_to_hostaddr_table0_cacheisol_d; |
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struct vth32_table **vaddr_to_hostaddr_table0_user; |
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struct vth32_table **vaddr_to_hostaddr_table0; /* should point to kernel or user */ |
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struct vth32_table *next_free_vth_table; |
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/* For 64-bit (generic) emulation: */ |
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unsigned char *(*fast_vaddr_to_hostaddr)(struct cpu *cpu, |
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uint64_t vaddr, int writeflag); |
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int bintrans_next_index; |
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int bintrans_data_writable[N_BINTRANS_VADDR_TO_HOST]; |
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uint64_t bintrans_data_vaddr[N_BINTRANS_VADDR_TO_HOST]; |
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unsigned char *bintrans_data_hostpage[N_BINTRANS_VADDR_TO_HOST]; |
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void (*bintrans_loadstore_32bit)(struct cpu *); /* Note: incorrect args */ |
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void (*bintrans_jump_to_32bit_pc)(struct cpu *); |
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void (*bintrans_simple_exception)(struct cpu *, int); |
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void (*bintrans_fast_rfe)(struct cpu *); |
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void (*bintrans_fast_eret)(struct cpu *); |
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void (*bintrans_fast_tlbwri)(struct cpu *, int); |
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void (*bintrans_fast_tlbpr)(struct cpu *, int); |
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#endif |
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#ifdef ENABLE_MIPS16 |
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int mips16; /* non-zero if MIPS16 code is allowed */ |
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uint16_t mips16_extend; /* set on 'extend' instructions to the entire 16-bit extend instruction */ |
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#endif |
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#ifdef ENABLE_INSTRUCTION_DELAYS |
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int instruction_delay; |
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#endif |
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int trace_tree_depth; |
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uint64_t delay_jmpaddr; /* only used if delay_slot > 0 */ |
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int delay_slot; |
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int nullify_next; /* set to 1 if next instruction |
int nullify_next; /* set to 1 if next instruction |
250 |
is to be nullified */ |
is to be nullified */ |
251 |
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/* This is set to non-zero, if it is possible at all that an |
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interrupt will occur. */ |
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int cached_interrupt_is_possible; |
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int show_trace_delay; /* 0=normal, > 0 = delay until show_trace */ |
int show_trace_delay; /* 0=normal, > 0 = delay until show_trace */ |
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uint64_t show_trace_addr; |
uint64_t show_trace_addr; |
254 |
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255 |
int last_was_jumptoself; |
int last_was_jumptoself; |
256 |
int jump_to_self_reg; |
int jump_to_self_reg; |
257 |
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#ifdef MFHILO_DELAY |
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int mfhi_delay; /* instructions since last mfhi */ |
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int mflo_delay; /* instructions since last mflo */ |
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#endif |
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int rmw; /* Read-Modify-Write */ |
int rmw; /* Read-Modify-Write */ |
259 |
int rmw_len; /* Length of rmw modification */ |
int rmw_len; /* Length of rmw modification */ |
260 |
uint64_t rmw_addr; /* Address of rmw modification */ |
uint64_t rmw_addr; /* Address of rmw modification */ |
261 |
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262 |
/* |
/* |
263 |
* TODO: The R5900 has 128-bit registers. I'm not really sure |
* NOTE: The R5900 has 128-bit registers. I'm not really sure |
264 |
* whether they are used a lot or not, at least with code produced |
* whether they are used a lot or not, at least with code produced |
265 |
* with gcc they are not. An important case however is lq and sq |
* with gcc they are not. An important case however is lq and sq |
266 |
* (load and store of 128-bit values). These "upper halves" of R5900 |
* (load and store of 128-bit values). These "upper halves" of R5900 |
267 |
* quadwords can be used in those cases. |
* quadwords can be used in those cases. |
268 |
* |
* |
269 |
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* hi1 and lo1 are the high 64-bit parts of the hi and lo registers. |
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* sa is a 32-bit "shift amount" register. |
271 |
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* |
272 |
* TODO: Generalize this. |
* TODO: Generalize this. |
273 |
*/ |
*/ |
274 |
uint64_t gpr_quadhi[N_MIPS_GPRS]; |
uint64_t gpr_quadhi[N_MIPS_GPRS]; |
275 |
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uint64_t hi1; |
276 |
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uint64_t lo1; |
277 |
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uint32_t r5900_sa; |
278 |
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279 |
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/* |
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* Statistics: |
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*/ |
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long stats_opcode[N_HI6]; |
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long stats__special[N_SPECIAL]; |
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long stats__regimm[N_REGIMM]; |
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long stats__special2[N_SPECIAL]; |
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/* Data and Instruction caches: */ |
/* Data and Instruction caches: */ |
281 |
unsigned char *cache[2]; |
unsigned char *cache[2]; |
282 |
void *cache_tags[2]; |
void *cache_tags[2]; |
285 |
int cache_linesize[2]; |
int cache_linesize[2]; |
286 |
int cache_mask[2]; |
int cache_mask[2]; |
287 |
int cache_miss_penalty[2]; |
int cache_miss_penalty[2]; |
288 |
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289 |
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/* Other stuff: */ |
290 |
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uint64_t cop0_config_select1; |
291 |
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292 |
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293 |
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/* NEW DYNTRANS: */ |
294 |
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295 |
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296 |
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/* |
297 |
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* Instruction translation cache and Virtual->Physical->Host |
298 |
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* address translation: |
299 |
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*/ |
300 |
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DYNTRANS_ITC(mips) |
301 |
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VPH_TLBS(mips,MIPS) |
302 |
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VPH32(mips,MIPS,uint64_t,uint8_t) |
303 |
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VPH64(mips,MIPS,uint8_t) |
304 |
}; |
}; |
305 |
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306 |
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307 |
/* cpu_mips.c: */ |
/* cpu_mips.c: */ |
308 |
struct cpu *mips_cpu_new(struct memory *mem, struct machine *machine, |
int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib); |
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int cpu_id, char *cpu_type_name); |
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void mips_cpu_show_full_statistics(struct machine *m); |
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309 |
void mips_cpu_tlbdump(struct machine *m, int x, int rawflag); |
void mips_cpu_tlbdump(struct machine *m, int x, int rawflag); |
310 |
void mips_cpu_register_match(struct machine *m, char *name, |
void mips_cpu_register_match(struct machine *m, char *name, |
311 |
int writeflag, uint64_t *valuep, int *match_register); |
int writeflag, uint64_t *valuep, int *match_register); |
312 |
void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs); |
void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs); |
313 |
int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
314 |
int running, uint64_t addr, int bintrans); |
int running, uint64_t addr); |
315 |
int mips_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr); |
int mips_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr); |
316 |
int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr); |
int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr); |
317 |
void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr, |
void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr, |
318 |
/* uint64_t pagemask, */ int coproc_nr, uint64_t vaddr_vpn2, |
/* uint64_t pagemask, */ int coproc_nr, uint64_t vaddr_vpn2, |
319 |
int vaddr_asid, int x_64); |
int vaddr_asid, int x_64); |
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void mips_cpu_cause_simple_exception(struct cpu *cpu, int exc_code); |
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320 |
int mips_cpu_run(struct emul *emul, struct machine *machine); |
int mips_cpu_run(struct emul *emul, struct machine *machine); |
321 |
void mips_cpu_dumpinfo(struct cpu *cpu); |
void mips_cpu_dumpinfo(struct cpu *cpu); |
322 |
void mips_cpu_list_available_types(void); |
void mips_cpu_list_available_types(void); |
329 |
uint64_t vaddr, uint64_t paddr0, uint64_t paddr1, |
uint64_t vaddr, uint64_t paddr0, uint64_t paddr1, |
330 |
int valid0, int valid1, int dirty0, int dirty1, int global, int asid, |
int valid0, int valid1, int dirty0, int dirty1, int global, int asid, |
331 |
int cachealgo0, int cachealgo1); |
int cachealgo0, int cachealgo1); |
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void update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void clear_all_chunks_from_all_tables(struct cpu *cpu); |
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void mips_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t paddr); |
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332 |
void coproc_register_read(struct cpu *cpu, |
void coproc_register_read(struct cpu *cpu, |
333 |
struct mips_coproc *cp, int reg_nr, uint64_t *ptr); |
struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select); |
334 |
void coproc_register_write(struct cpu *cpu, |
void coproc_register_write(struct cpu *cpu, |
335 |
struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int flag64); |
struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int flag64, |
336 |
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int select); |
337 |
void coproc_tlbpr(struct cpu *cpu, int readflag); |
void coproc_tlbpr(struct cpu *cpu, int readflag); |
338 |
void coproc_tlbwri(struct cpu *cpu, int randomflag); |
void coproc_tlbwri(struct cpu *cpu, int randomflag); |
339 |
void coproc_rfe(struct cpu *cpu); |
void coproc_rfe(struct cpu *cpu); |
348 |
int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
349 |
unsigned char *data, size_t len, int writeflag, int cache_flags); |
unsigned char *data, size_t len, int writeflag, int cache_flags); |
350 |
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351 |
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int translate_v2p_mmu3k(struct cpu *cpu, uint64_t vaddr, |
352 |
/* mips16.c: */ |
uint64_t *return_addr, int flags); |
353 |
int mips16_to_32(struct cpu *cpu, unsigned char *instr16, unsigned char *instr); |
int translate_v2p_mmu8k(struct cpu *cpu, uint64_t vaddr, |
354 |
|
uint64_t *return_addr, int flags); |
355 |
|
int translate_v2p_mmu10k(struct cpu *cpu, uint64_t vaddr, |
356 |
|
uint64_t *return_addr, int flags); |
357 |
|
int translate_v2p_mmu4100(struct cpu *cpu, uint64_t vaddr, |
358 |
|
uint64_t *return_addr, int flags); |
359 |
|
int translate_v2p_generic(struct cpu *cpu, uint64_t vaddr, |
360 |
|
uint64_t *return_addr, int flags); |
361 |
|
|
362 |
|
|
363 |
|
/* Dyntrans unaligned load/store: */ |
364 |
|
void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic, |
365 |
|
int is_left, int wlen, int store); |
366 |
|
|
367 |
|
|
368 |
|
void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
369 |
|
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
370 |
|
void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
371 |
|
void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
372 |
|
void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
373 |
|
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
374 |
|
void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
375 |
|
void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
376 |
|
|
377 |
|
|
378 |
#endif /* CPU_MIPS_H */ |
#endif /* CPU_MIPS_H */ |