Parent Directory | Revision Log
++ trunk/HISTORY (local) $Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $ 20060816 Adding a framework for emulated/virtual timers (src/timer.c), using only setitimer(). Rewriting the mc146818 to use the new timer framework. 20060817 Adding a call to gettimeofday() every now and then (once every second, at the moment) to resynch the timer if it drifts. Beginning to convert the ISA timer interrupt mechanism (8253 and 8259) to use the new timer framework. Removing the -I command line option. 20060819 Adding the -I command line option again, with new semantics. Working on Footbridge timer interrupts; NetBSD/NetWinder and NetBSD/CATS now run at correct speed, but unfortunately with HUGE delays during bootup. 20060821 Some minor m68k updates. Adding the first instruction: nop. :) Minor Alpha emulation updates. 20060822 Adding a FreeBSD development specific YAMON environment variable ("khz") (as suggested by Bruce M. Simpson). Moving YAMON environment variable initialization from machine_evbmips.c into promemul/yamon.c, and adding some more variables. Continuing on the LCA PCI bus controller (for Alpha machines). 20060823 Continuing on the timer stuff: experimenting with MIPS count/ compare interrupts connected to the timer framework. 20060825 Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and 0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer, to allow NetBSD/pmax 4.0_BETA to be installed from CDROM. Minor updates to the LCA PCI controller. 20060827 Implementing a CHIP8 cpu mode, and a corresponding CHIP8 machine, for fun. Disassembly support for all instructions, and most of the common instructions have been implemented: mvi, mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr, skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub, font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne. 20060828 Beginning to convert the CHIP8 cpu in the CHIP8 machine to a (more correct) RCA 180x cpu. (Disassembly for all 1802 instructions has been implemented, but no execution yet, and no 1805 extended instructions.) 20060829 Minor Alpha emulation updates. 20060830 Beginning to experiment a little with PCI IDE for SGI O2. Fixing the cursor key mappings for MobilePro 770 emulation. Fixing the LK201 warning caused by recent NetBSD/pmax. The MIPS R41xx standby, suspend, and hibernate instructions now behave like the RM52xx/MIPS32/MIPS64 wait instruction. Fixing dev_wdc so it calculates correct (64-bit) offsets before giving them to diskimage_access(). 20060831 Continuing on Alpha emulation (OSF1 PALcode). 20060901 Minor Alpha updates; beginning on virtual memory pagetables. Removed the limit for max nr of devices (in preparation for allowing devices' base addresses to be changed during runtime). Adding a hack for MIPS [d]mfc0 select 0 (except the count register), so that the coproc register is simply copied. The MIPS suspend instruction now exits the emulator, instead of being treated as a wait instruction (this causes NetBSD/ hpcmips to get correct 'halt' behavior). The VR41xx RTC now returns correct time. Connecting the VR41xx timer to the timer framework (fixed at 128 Hz, for now). Continuing on SPARC emulation, adding more instructions: restore, ba_xcc, ble. The rectangle drawing demo works :) Removing the last traces of the old ENABLE_CACHE_EMULATION MIPS stuff (not usable with dyntrans anyway). 20060902 Splitting up src/net.c into several smaller files in its own subdirectory (src/net/). 20060903 Cleanup of the files in src/net/, to make them less ugly. 20060904 Continuing on the 'settings' subsystem. Minor progress on the SPARC emulation mode. 20060905 Cleanup of various things, and connecting the settings infrastructure to various subsystems (emul, machine, cpu, etc). Changing the lk201 mouse update routine to not rely on any emulated hardware framebuffer cursor coordinates, but instead always do (semi-usable) relative movements. 20060906 Continuing on the lk201 mouse stuff. Mouse behaviour with multiple framebuffers (which was working in Ultrix) is now semi-broken (but it still works, in a way). Moving the documentation about networking into its own file (networking.html), and refreshing it a bit. Adding an example of how to use ethernet frame direct-access (udp_snoop). 20060907 Continuing on the settings infrastructure. 20060908 Minor updates to SH emulation: for 32-bit emulation: delay slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on ice, for now. 20060909-10 Implementing some more 32-bit SH instructions. Removing the 64-bit mode completely. Enough has now been implemented to run the rectangle drawing demo. :-) 20060912 Adding more SH instructions. 20060916 Continuing on SH emulation (some more instructions: div0u, div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett, tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac). Continuing on the settings subsystem (beginning on reading/ writing settings, removing bugs, and connecting more cpus to the framework). 20060919 More work on SH emulation; adding an ldc banked instruction, and attaching a 640x480 framebuffer to the Dreamcast machine mode (NetBSD/dreamcast prints the NetBSD copyright banner :-), and then panics). 20060920 Continuing on the settings subsystem. 20060921 Fixing the Footbridge timer stuff so that NetBSD/cats and NetBSD/netwinder boot up without the delays. 20060922 Temporarily hardcoding MIPS timer interrupt to 100 Hz. With 'wait' support disabled, NetBSD/malta and Linux/malta run at correct speed. 20060923 Connecting dev_gt to the timer framework, so that NetBSD/cobalt runs at correct speed. Moving SH4-specific memory mapped registers into its own device (dev_sh4.c). Running with -N now prints "idling" instead of bogus nr of instrs/second (which isn't valid anyway) while idling. 20060924 Algor emulation should now run at correct speed. Adding disassembly support for some MIPS64 revision 2 instructions: ext, dext, dextm, dextu. 20060926 The timer framework now works also when the MIPS wait instruction is used. 20060928 Re-implementing checks for coprocessor availability for MIPS cop0 instructions. (Thanks to Carl van Schaik for noticing the lack of cop0 availability checks.) 20060929 Implementing an instruction combination hack which treats NetBSD/pmax' idle loop as a wait-like instruction. 20060930 The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c, causing TLB lookups to sometimes succeed when they should have failed. (A big thank you to Juli Mallett for noticing the problem.) Adding disassembly support for more MIPS64 revision 2 opcodes (seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu, dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also implementing seb, seh, dsbh, dshd, and wsbh. Implementing an instruction combination hack for Linux/pmax' idle loop, similar to the NetBSD/pmax case. 20061001 Changing the NetBSD/sgimips install instructions to extract files from an iso image, instead of downloading them via ftp. 20061002 More-than-31-bit userland addresses in memory_mips_v2p.c were not actually working; applying a fix from Carl van Schaik to enable them to work + making some other updates (adding kuseg support). Fixing hpcmips (vr41xx) timer initialization. Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup loop. Seems to work both for R3000 and non-R3000. 20061003 Continuing a little on SH emulation (adding more control registers; mini-cleanup of memory_sh.c). 20061004 Beginning on a dev_rtc, a clock/timer device for the test machines; also adding a demo, and some documentation. Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't sign-extended), and adding the addc and ldtlb instructions. 20061005 Contining on SH emulation: virtual to physical address translation, and a skeleton exception mechanism. 20061006 Adding more SH instructions (various loads and stores, rte, negc, muls.w, various privileged register-move instructions). 20061007 More SH instructions: various move instructions, trapa, div0s, float, fdiv, ftrc. Continuing on dev_rtc; removing the rtc demo. 20061008 Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast programs using KOS libs need this.) Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca, fmul, fadd, various floating-point moves, etc. A 256-byte demo for Dreamcast runs :-) 20061012 Adding the SH "lds Rm,pr" and bsr instructions. 20061013 More SH instructions: "sts fpscr,rn", tas.b, and some more floating point instructions, cmp/str, and more moves. Adding a dummy dev_pvr (Dreamcast graphics controller). 20061014 Generalizing the expression evaluator (used in the built-in debugger) to support parentheses and +-*/%^&|. 20061015 Removing the experimental tlb index hint code in mips_memory_v2p.c, since it didn't really have any effect. 20061017 Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg, frchg, and some other instructions. Fixing missing sign- extension in an 8-bit load instruction. 20061019 Adding a simple dev_dreamcast_rtc. Implementing memory-mapped access to the SH ITLB/UTLB arrays. 20061021 Continuing on various SH and Dreamcast things: sh4 timers, debug messages for dev_pvr, fixing some virtual address translation bugs, adding the bsrf instruction. The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :) Adding a dummy dev_dreamcast_asic.c (not really useful yet). Implementing simple support for Store Queues. Beginning on the PVR Tile Accelerator. 20061022 Generalizing the PVR framebuffer to support off-screen drawing, multiple bit-depths, etc. (A small speed penalty, but most likely worth it.) Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac, fschg, and some more); correcting bugs in "fsca" and "float". 20061024 Adding the SH ftrv (matrix * vector) instruction. Marcus Comstedt's "tatest" example runs :) (wireframe only). Correcting disassembly for SH floating point instructions that use the xd* registers. Adding the SH fsts instruction. In memory_device_dyntrans_access(), only the currently used range is now invalidated, and not the entire device range. 20061025 Adding a dummy AVR32 cpu mode skeleton. 20061026 Various Dreamcast updates; beginning on a Maple bus controller. 20061027 Continuing on the Maple bus. A bogus Controller, Keyboard, and Mouse can now be detected by NetBSD and KOS homebrew programs. Cleaning up the SH4 Timer Management Unit, and beginning on SH4 interrupts. Implementing the Dreamcast SYSASIC. 20061028 Continuing on the SYSASIC. Adding the SH fsqrt instruction. memory_sh.c now actually scans the ITLB. Fixing a bug in dev_sh4.c, related to associative writes into the memory-mapped UTLB array. NetBSD/dreamcast now reaches userland stably, and prints the "Terminal type?" message :-] Implementing enough of the Dreamcast keyboard to make NetBSD accept it for input. Enabling SuperH for stable (non-development) builds. Adding NetBSD/dreamcast to the documentation, although it doesn't support root-on-nfs yet. 20061029 Changing usleep(1) calls in the debugger to to usleep(10000) (according to Brian Foley, this makes GXemul run better on MacOS X). Making the Maple "Controller" do something (enough to barely interact with dcircus.elf). 20061030-31 Some progress on the PVR. More test programs start running (but with strange output). Various other SH4-related updates. 20061102 Various Dreamcast and SH4 updates; more KOS demos run now. 20061104 Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter). 20061105 Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0. Testing for the release. ============== RELEASE 0.4.3 ==============
1 | #ifndef CPU_MIPS_H |
2 | #define CPU_MIPS_H |
3 | |
4 | /* |
5 | * Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions are met: |
9 | * |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
15 | * 3. The name of the author may not be used to endorse or promote products |
16 | * derived from this software without specific prior written permission. |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
19 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
24 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
26 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
28 | * SUCH DAMAGE. |
29 | * |
30 | * |
31 | * $Id: cpu_mips.h,v 1.50 2006/10/14 23:47:37 debug Exp $ |
32 | */ |
33 | |
34 | #include "misc.h" |
35 | |
36 | struct cpu_family; |
37 | struct emul; |
38 | struct machine; |
39 | struct timer; |
40 | |
41 | /* |
42 | * CPU type definitions: See mips_cpu_types.h. |
43 | */ |
44 | |
45 | struct mips_cpu_type_def { |
46 | char *name; |
47 | int rev; |
48 | int sub; |
49 | char flags; |
50 | char exc_model; /* EXC3K or EXC4K */ |
51 | char mmu_model; /* MMU3K or MMU4K */ |
52 | char isa_level; /* 1, 2, 3, 4, 5, 32, 64 */ |
53 | char isa_revision; /* 1 or 2 (for MIPS32/64) */ |
54 | int nr_of_tlb_entries; /* 32, 48, 64, ... */ |
55 | char instrs_per_cycle; /* simplified, 1, 2, or 4 */ |
56 | int picache; |
57 | int pilinesize; |
58 | int piways; |
59 | int pdcache; |
60 | int pdlinesize; |
61 | int pdways; |
62 | int scache; |
63 | int slinesize; |
64 | int sways; |
65 | }; |
66 | |
67 | #define INITIAL_PC 0xffffffffbfc00000ULL |
68 | #define INITIAL_STACK_POINTER (0xffffffffa0008000ULL - 256) |
69 | |
70 | |
71 | /* |
72 | * Coproc 0: |
73 | * |
74 | * NOTE: |
75 | * On R3000, only hi and lo0 are used, and then only the lowest 32 bits. |
76 | */ |
77 | #define N_MIPS_COPROC_REGS 32 |
78 | struct mips_tlb { |
79 | uint64_t hi; |
80 | uint64_t lo0; |
81 | uint64_t lo1; |
82 | uint64_t mask; |
83 | }; |
84 | |
85 | |
86 | /* |
87 | * Coproc 1: |
88 | */ |
89 | /* FPU control registers: */ |
90 | #define N_MIPS_FCRS 32 |
91 | #define MIPS_FPU_FCIR 0 |
92 | #define MIPS_FPU_FCCR 25 |
93 | #define MIPS_FPU_FCSR 31 |
94 | #define MIPS_FCSR_FCC0_SHIFT 23 |
95 | #define MIPS_FCSR_FCC1_SHIFT 25 |
96 | |
97 | #define N_VADDR_TO_TLB_INDEX_ENTRIES (1 << 20) |
98 | |
99 | struct mips_coproc { |
100 | int coproc_nr; |
101 | uint64_t reg[N_MIPS_COPROC_REGS]; |
102 | |
103 | /* Only for COP0: */ |
104 | struct mips_tlb *tlbs; |
105 | int nr_of_tlbs; |
106 | |
107 | /* Only for COP1: floating point control registers */ |
108 | /* (Maybe also for COP0?) */ |
109 | uint64_t fcr[N_MIPS_FCRS]; |
110 | }; |
111 | |
112 | #define N_MIPS_COPROCS 4 |
113 | |
114 | #define N_MIPS_GPRS 32 /* General purpose registers */ |
115 | #define N_MIPS_FPRS 32 /* Floating point registers */ |
116 | |
117 | /* |
118 | * These should all be 2 characters wide: |
119 | * |
120 | * NOTE: These are for 32-bit ABIs. For the 64-bit ABI, registers 8..11 |
121 | * are used to pass arguments and are then called "a4".."a7". |
122 | * |
123 | * TODO: Should there be two different variants of this? It's not really |
124 | * possible to figure out in some easy way if the code running was |
125 | * written for a 32-bit or 64-bit ABI. |
126 | */ |
127 | #define MIPS_REGISTER_NAMES { \ |
128 | "zr", "at", "v0", "v1", "a0", "a1", "a2", "a3", \ |
129 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \ |
130 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \ |
131 | "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra" } |
132 | |
133 | #define MIPS_GPR_ZERO 0 /* zero */ |
134 | #define MIPS_GPR_AT 1 /* at */ |
135 | #define MIPS_GPR_V0 2 /* v0 */ |
136 | #define MIPS_GPR_V1 3 /* v1 */ |
137 | #define MIPS_GPR_A0 4 /* a0 */ |
138 | #define MIPS_GPR_A1 5 /* a1 */ |
139 | #define MIPS_GPR_A2 6 /* a2 */ |
140 | #define MIPS_GPR_A3 7 /* a3 */ |
141 | #define MIPS_GPR_T0 8 /* t0 */ |
142 | #define MIPS_GPR_T1 9 /* t1 */ |
143 | #define MIPS_GPR_T2 10 /* t2 */ |
144 | #define MIPS_GPR_T3 11 /* t3 */ |
145 | #define MIPS_GPR_T4 12 /* t4 */ |
146 | #define MIPS_GPR_T5 13 /* t5 */ |
147 | #define MIPS_GPR_T6 14 /* t6 */ |
148 | #define MIPS_GPR_T7 15 /* t7 */ |
149 | #define MIPS_GPR_S0 16 /* s0 */ |
150 | #define MIPS_GPR_S1 17 /* s1 */ |
151 | #define MIPS_GPR_S2 18 /* s2 */ |
152 | #define MIPS_GPR_S3 19 /* s3 */ |
153 | #define MIPS_GPR_S4 20 /* s4 */ |
154 | #define MIPS_GPR_S5 21 /* s5 */ |
155 | #define MIPS_GPR_S6 22 /* s6 */ |
156 | #define MIPS_GPR_S7 23 /* s7 */ |
157 | #define MIPS_GPR_T8 24 /* t8 */ |
158 | #define MIPS_GPR_T9 25 /* t9 */ |
159 | #define MIPS_GPR_K0 26 /* k0 */ |
160 | #define MIPS_GPR_K1 27 /* k1 */ |
161 | #define MIPS_GPR_GP 28 /* gp */ |
162 | #define MIPS_GPR_SP 29 /* sp */ |
163 | #define MIPS_GPR_FP 30 /* fp */ |
164 | #define MIPS_GPR_RA 31 /* ra */ |
165 | |
166 | #define N_HI6 64 |
167 | #define N_SPECIAL 64 |
168 | #define N_REGIMM 32 |
169 | |
170 | |
171 | /* An "impossible" paddr: */ |
172 | #define IMPOSSIBLE_PADDR 0x1212343456566767ULL |
173 | |
174 | #define DEFAULT_PCACHE_SIZE 15 /* 32 KB */ |
175 | #define DEFAULT_PCACHE_LINESIZE 5 /* 32 bytes */ |
176 | |
177 | struct r3000_cache_line { |
178 | uint32_t tag_paddr; |
179 | int tag_valid; |
180 | }; |
181 | #define R3000_TAG_VALID 1 |
182 | #define R3000_TAG_DIRTY 2 |
183 | |
184 | struct r4000_cache_line { |
185 | char dummy; |
186 | }; |
187 | |
188 | |
189 | #ifdef ONEKPAGE |
190 | #define MIPS_IC_ENTRIES_SHIFT 8 |
191 | #else |
192 | #define MIPS_IC_ENTRIES_SHIFT 10 |
193 | #endif |
194 | |
195 | #define MIPS_N_IC_ARGS 3 |
196 | #define MIPS_INSTR_ALIGNMENT_SHIFT 2 |
197 | #define MIPS_IC_ENTRIES_PER_PAGE (1 << MIPS_IC_ENTRIES_SHIFT) |
198 | #define MIPS_PC_TO_IC_ENTRY(a) (((a)>>MIPS_INSTR_ALIGNMENT_SHIFT) \ |
199 | & (MIPS_IC_ENTRIES_PER_PAGE-1)) |
200 | #define MIPS_ADDR_TO_PAGENR(a) ((a) >> (MIPS_IC_ENTRIES_SHIFT \ |
201 | + MIPS_INSTR_ALIGNMENT_SHIFT)) |
202 | |
203 | #define MIPS_L2N 17 |
204 | #define MIPS_L3N 18 |
205 | |
206 | #define MIPS_MAX_VPH_TLB_ENTRIES 192 |
207 | DYNTRANS_MISC_DECLARATIONS(mips,MIPS,uint64_t) |
208 | DYNTRANS_MISC64_DECLARATIONS(mips,MIPS,uint8_t) |
209 | |
210 | |
211 | struct mips_cpu { |
212 | struct mips_cpu_type_def cpu_type; |
213 | |
214 | /* General purpose registers: */ |
215 | uint64_t gpr[N_MIPS_GPRS]; |
216 | |
217 | /* Dummy destination register when writing to the zero register: */ |
218 | uint64_t scratch; |
219 | |
220 | /* Special purpose registers: */ |
221 | uint64_t hi; |
222 | uint64_t lo; |
223 | |
224 | /* Coprocessors: */ |
225 | struct mips_coproc *coproc[N_MIPS_COPROCS]; |
226 | uint64_t cop0_config_select1; |
227 | |
228 | int last_written_tlb_index; |
229 | |
230 | /* Count/compare timer: */ |
231 | int compare_register_set; |
232 | int compare_interrupts_pending; |
233 | struct timer *timer; |
234 | |
235 | int rmw; /* Read-Modify-Write */ |
236 | int rmw_len; /* Length of rmw modification */ |
237 | uint64_t rmw_addr; /* Address of rmw modification */ |
238 | |
239 | /* |
240 | * NOTE: The R5900 has 128-bit registers. I'm not really sure |
241 | * whether they are used a lot or not, at least with code produced |
242 | * with gcc they are not. An important case however is lq and sq |
243 | * (load and store of 128-bit values). These "upper halves" of R5900 |
244 | * quadwords can be used in those cases. |
245 | * |
246 | * hi1 and lo1 are the high 64-bit parts of the hi and lo registers. |
247 | * sa is a 32-bit "shift amount" register. |
248 | * |
249 | * TODO: Generalize this. |
250 | */ |
251 | uint64_t gpr_quadhi[N_MIPS_GPRS]; |
252 | uint64_t hi1; |
253 | uint64_t lo1; |
254 | uint32_t r5900_sa; |
255 | |
256 | /* Data and Instruction caches: */ |
257 | unsigned char *cache[2]; |
258 | void *cache_tags[2]; |
259 | uint64_t cache_last_paddr[2]; |
260 | int cache_size[2]; |
261 | int cache_linesize[2]; |
262 | int cache_mask[2]; |
263 | int cache_miss_penalty[2]; |
264 | |
265 | |
266 | /* |
267 | * Instruction translation cache and Virtual->Physical->Host |
268 | * address translation: |
269 | */ |
270 | DYNTRANS_ITC(mips) |
271 | VPH_TLBS(mips,MIPS) |
272 | VPH32(mips,MIPS,uint64_t,uint8_t) |
273 | VPH64(mips,MIPS,uint8_t) |
274 | }; |
275 | |
276 | |
277 | /* cpu_mips.c: */ |
278 | int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib); |
279 | void mips_cpu_tlbdump(struct machine *m, int x, int rawflag); |
280 | void mips_cpu_register_match(struct machine *m, char *name, |
281 | int writeflag, uint64_t *valuep, int *match_register); |
282 | void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs); |
283 | int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
284 | int running, uint64_t addr); |
285 | int mips_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr); |
286 | int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr); |
287 | void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr, |
288 | /* uint64_t pagemask, */ int coproc_nr, uint64_t vaddr_vpn2, |
289 | int vaddr_asid, int x_64); |
290 | int mips_cpu_run(struct emul *emul, struct machine *machine); |
291 | void mips_cpu_dumpinfo(struct cpu *cpu); |
292 | void mips_cpu_list_available_types(void); |
293 | int mips_cpu_family_init(struct cpu_family *); |
294 | |
295 | |
296 | /* cpu_mips_coproc.c: */ |
297 | struct mips_coproc *mips_coproc_new(struct cpu *cpu, int coproc_nr); |
298 | void mips_coproc_tlb_set_entry(struct cpu *cpu, int entrynr, int size, |
299 | uint64_t vaddr, uint64_t paddr0, uint64_t paddr1, |
300 | int valid0, int valid1, int dirty0, int dirty1, int global, int asid, |
301 | int cachealgo0, int cachealgo1); |
302 | void coproc_register_read(struct cpu *cpu, |
303 | struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select); |
304 | void coproc_register_write(struct cpu *cpu, |
305 | struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int flag64, |
306 | int select); |
307 | void coproc_tlbpr(struct cpu *cpu, int readflag); |
308 | void coproc_tlbwri(struct cpu *cpu, int randomflag); |
309 | void coproc_rfe(struct cpu *cpu); |
310 | void coproc_eret(struct cpu *cpu); |
311 | void coproc_function(struct cpu *cpu, struct mips_coproc *cp, int cpnr, |
312 | uint32_t function, int unassemble_only, int running); |
313 | |
314 | |
315 | /* memory_mips.c: */ |
316 | int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr, |
317 | int writeflag, size_t len, unsigned char *data); |
318 | int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
319 | unsigned char *data, size_t len, int writeflag, int cache_flags); |
320 | |
321 | int translate_v2p_mmu3k(struct cpu *cpu, uint64_t vaddr, |
322 | uint64_t *return_addr, int flags); |
323 | int translate_v2p_mmu8k(struct cpu *cpu, uint64_t vaddr, |
324 | uint64_t *return_addr, int flags); |
325 | int translate_v2p_mmu10k(struct cpu *cpu, uint64_t vaddr, |
326 | uint64_t *return_addr, int flags); |
327 | int translate_v2p_mmu4100(struct cpu *cpu, uint64_t vaddr, |
328 | uint64_t *return_addr, int flags); |
329 | int translate_v2p_generic(struct cpu *cpu, uint64_t vaddr, |
330 | uint64_t *return_addr, int flags); |
331 | |
332 | |
333 | /* Dyntrans unaligned load/store: */ |
334 | void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic, |
335 | int is_left, int wlen, int store); |
336 | |
337 | |
338 | int mips_run_instr(struct cpu *cpu); |
339 | void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
340 | unsigned char *host_page, int writeflag, uint64_t paddr_page); |
341 | void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
342 | void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
343 | int mips32_run_instr(struct cpu *cpu); |
344 | void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
345 | unsigned char *host_page, int writeflag, uint64_t paddr_page); |
346 | void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
347 | void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
348 | |
349 | |
350 | #endif /* CPU_MIPS_H */ |
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