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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
30 |
* |
* |
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* $Id: cpu_mips.h,v 1.45 2006/07/16 13:32:27 debug Exp $ |
* $Id: cpu_mips.h,v 1.50 2006/10/14 23:47:37 debug Exp $ |
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*/ |
*/ |
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#include "misc.h" |
#include "misc.h" |
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struct cpu_family; |
struct cpu_family; |
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struct emul; |
struct emul; |
38 |
struct machine; |
struct machine; |
39 |
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struct timer; |
40 |
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41 |
/* |
/* |
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* CPU type definitions: See mips_cpu_types.h. |
* CPU type definitions: See mips_cpu_types.h. |
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#define MIPS_FCSR_FCC0_SHIFT 23 |
#define MIPS_FCSR_FCC0_SHIFT 23 |
95 |
#define MIPS_FCSR_FCC1_SHIFT 25 |
#define MIPS_FCSR_FCC1_SHIFT 25 |
96 |
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97 |
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#define N_VADDR_TO_TLB_INDEX_ENTRIES (1 << 20) |
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struct mips_coproc { |
struct mips_coproc { |
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int coproc_nr; |
int coproc_nr; |
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uint64_t reg[N_MIPS_COPROC_REGS]; |
uint64_t reg[N_MIPS_COPROC_REGS]; |
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#define N_SPECIAL 64 |
#define N_SPECIAL 64 |
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#define N_REGIMM 32 |
#define N_REGIMM 32 |
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/******************************* OLD: *****************************/ |
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/* An "impossible" paddr: */ |
/* An "impossible" paddr: */ |
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#define IMPOSSIBLE_PADDR 0x1212343456566767ULL |
#define IMPOSSIBLE_PADDR 0x1212343456566767ULL |
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char dummy; |
char dummy; |
186 |
}; |
}; |
187 |
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/********************************************************************/ |
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188 |
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189 |
#ifdef ONEKPAGE |
#ifdef ONEKPAGE |
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#define MIPS_IC_ENTRIES_SHIFT 8 |
#define MIPS_IC_ENTRIES_SHIFT 8 |
203 |
#define MIPS_L2N 17 |
#define MIPS_L2N 17 |
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#define MIPS_L3N 18 |
#define MIPS_L3N 18 |
205 |
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|
206 |
#define MIPS_MAX_VPH_TLB_ENTRIES 128 |
#define MIPS_MAX_VPH_TLB_ENTRIES 192 |
207 |
DYNTRANS_MISC_DECLARATIONS(mips,MIPS,uint64_t) |
DYNTRANS_MISC_DECLARATIONS(mips,MIPS,uint64_t) |
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DYNTRANS_MISC64_DECLARATIONS(mips,MIPS,uint8_t) |
DYNTRANS_MISC64_DECLARATIONS(mips,MIPS,uint8_t) |
209 |
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#if 0 |
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struct mips_instr_call { |
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void (*f)(struct cpu *, struct mips_instr_call *); |
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size_t arg[MIPS_N_IC_ARGS]; |
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}; |
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/* Translation cache struct for each physical page: */ |
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struct mips_tc_physpage { |
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struct mips_instr_call ics[MIPS_IC_ENTRIES_PER_PAGE + 3]; |
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uint32_t next_ofs; /* or 0 for end of chain */ |
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int flags; |
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uint64_t physaddr; |
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}; |
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struct mips_vpg_tlb_entry { |
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uint8_t valid; |
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uint8_t writeflag; |
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unsigned char *host_page; |
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int64_t timestamp; |
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uint64_t vaddr_page; |
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uint64_t paddr_page; |
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}; |
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#endif |
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/********************************************************************/ |
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210 |
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211 |
struct mips_cpu { |
struct mips_cpu { |
212 |
struct mips_cpu_type_def cpu_type; |
struct mips_cpu_type_def cpu_type; |
213 |
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214 |
struct mips_coproc *coproc[N_MIPS_COPROCS]; |
/* General purpose registers: */ |
215 |
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uint64_t gpr[N_MIPS_GPRS]; |
216 |
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217 |
int compare_register_set; |
/* Dummy destination register when writing to the zero register: */ |
218 |
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uint64_t scratch; |
219 |
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|
220 |
/* Special purpose registers: */ |
/* Special purpose registers: */ |
221 |
uint64_t hi; |
uint64_t hi; |
222 |
uint64_t lo; |
uint64_t lo; |
223 |
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|
224 |
/* Dummy destination register when writing to the zero register: */ |
/* Coprocessors: */ |
225 |
uint64_t scratch; |
struct mips_coproc *coproc[N_MIPS_COPROCS]; |
226 |
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uint64_t cop0_config_select1; |
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/* General purpose registers: */ |
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uint64_t gpr[N_MIPS_GPRS]; |
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int nullify_next; /* set to 1 if next instruction |
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is to be nullified */ |
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227 |
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228 |
int show_trace_delay; /* 0=normal, > 0 = delay until show_trace */ |
int last_written_tlb_index; |
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uint64_t show_trace_addr; |
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229 |
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230 |
int last_was_jumptoself; |
/* Count/compare timer: */ |
231 |
int jump_to_self_reg; |
int compare_register_set; |
232 |
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int compare_interrupts_pending; |
233 |
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struct timer *timer; |
234 |
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235 |
int rmw; /* Read-Modify-Write */ |
int rmw; /* Read-Modify-Write */ |
236 |
int rmw_len; /* Length of rmw modification */ |
int rmw_len; /* Length of rmw modification */ |
253 |
uint64_t lo1; |
uint64_t lo1; |
254 |
uint32_t r5900_sa; |
uint32_t r5900_sa; |
255 |
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256 |
/* Data and Instruction caches: */ |
/* Data and Instruction caches: */ |
257 |
unsigned char *cache[2]; |
unsigned char *cache[2]; |
258 |
void *cache_tags[2]; |
void *cache_tags[2]; |
262 |
int cache_mask[2]; |
int cache_mask[2]; |
263 |
int cache_miss_penalty[2]; |
int cache_miss_penalty[2]; |
264 |
|
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/* Other stuff: */ |
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uint64_t cop0_config_select1; |
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/* NEW DYNTRANS: */ |
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265 |
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266 |
/* |
/* |
267 |
* Instruction translation cache and Virtual->Physical->Host |
* Instruction translation cache and Virtual->Physical->Host |