/[gxemul]/trunk/src/include/cpu_mips.h
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revision 4 by dpavlin, Mon Oct 8 16:18:00 2007 UTC revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC
# Line 2  Line 2 
2  #define CPU_MIPS_H  #define CPU_MIPS_H
3    
4  /*  /*
5   *  Copyright (C) 2003-2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2003-2006  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_mips.h,v 1.13 2005/03/14 12:49:16 debug Exp $   *  $Id: cpu_mips.h,v 1.26 2006/02/13 04:23:25 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
# Line 57  struct mips_cpu_type_def { Line 57  struct mips_cpu_type_def {
57          char            isa_level;              /*  1, 2, 3, 4, 5, 32, 64  */          char            isa_level;              /*  1, 2, 3, 4, 5, 32, 64  */
58          int             nr_of_tlb_entries;      /*  32, 48, 64, ...  */          int             nr_of_tlb_entries;      /*  32, 48, 64, ...  */
59          char            instrs_per_cycle;       /*  simplified, 1, 2, or 4  */          char            instrs_per_cycle;       /*  simplified, 1, 2, or 4  */
60          int             default_picache;          int             picache;
61          int             default_pdcache;          int             pilinesize;
62          int             default_pilinesize;          int             piways;
63          int             default_pdlinesize;          int             pdcache;
64          int             default_scache;          int             pdlinesize;
65          int             default_slinesize;          int             pdways;
66            int             scache;
67            int             slinesize;
68            int             sways;
69  };  };
70    
71  #define INITIAL_PC                      0xffffffffbfc00000ULL  #define INITIAL_PC                      0xffffffffbfc00000ULL
# Line 154  struct mips_coproc { Line 157  struct mips_coproc {
157  #define MIPS_GPR_RA             31              /*  ra  */  #define MIPS_GPR_RA             31              /*  ra  */
158    
159  /*  Meaning of delay_slot:  */  /*  Meaning of delay_slot:  */
160  #define NOT_DELAYED             0  #define NOT_DELAYED                     0
161  #define DELAYED                 1  #define DELAYED                         1
162  #define TO_BE_DELAYED           2  #define TO_BE_DELAYED                   2
163    #define EXCEPTION_IN_DELAY_SLOT         0x100
164    
165  #define N_HI6                   64  #define N_HI6                   64
166  #define N_SPECIAL               64  #define N_SPECIAL               64
167  #define N_REGIMM                32  #define N_REGIMM                32
168    
169    /*******************************  OLD:  *****************************/
170    
171  /*  Number of "tiny" translation cache entries:  */  /*  Number of "tiny" translation cache entries:  */
172  #define N_TRANSLATION_CACHE_INSTR       5  #define N_TRANSLATION_CACHE_INSTR       5
173  #define N_TRANSLATION_CACHE_DATA        5  #define N_TRANSLATION_CACHE_DATA        5
# Line 193  struct r4000_cache_line { Line 199  struct r4000_cache_line {
199          char            dummy;          char            dummy;
200  };  };
201    
202    /********************************************************************/
203    
204    #ifdef ONEKPAGE
205    #define MIPS_IC_ENTRIES_SHIFT           8
206    #else
207    #define MIPS_IC_ENTRIES_SHIFT           10
208    #endif
209    
210    #define MIPS_N_IC_ARGS                  3
211    #define MIPS_INSTR_ALIGNMENT_SHIFT      2
212    #define MIPS_IC_ENTRIES_PER_PAGE        (1 << MIPS_IC_ENTRIES_SHIFT)
213    #define MIPS_PC_TO_IC_ENTRY(a)          (((a)>>MIPS_INSTR_ALIGNMENT_SHIFT) \
214                                            & (MIPS_IC_ENTRIES_PER_PAGE-1))
215    #define MIPS_ADDR_TO_PAGENR(a)          ((a) >> (MIPS_IC_ENTRIES_SHIFT \
216                                            + MIPS_INSTR_ALIGNMENT_SHIFT))
217    
218    struct mips_instr_call {
219            void    (*f)(struct cpu *, struct mips_instr_call *);
220            size_t  arg[MIPS_N_IC_ARGS];
221    };
222    
223    /*  Translation cache struct for each physical page:  */
224    struct mips_tc_physpage {
225            struct mips_instr_call ics[MIPS_IC_ENTRIES_PER_PAGE + 3];
226            uint32_t        next_ofs;       /*  or 0 for end of chain  */
227            int             flags;
228            uint64_t        physaddr;
229    };
230    
231    #define MIPS_MAX_VPH_TLB_ENTRIES        128
232    struct mips_vpg_tlb_entry {
233            uint8_t         valid;
234            uint8_t         writeflag;
235            unsigned char   *host_page;
236            int64_t         timestamp;
237            uint64_t        vaddr_page;
238            uint64_t        paddr_page;
239    };
240    
241    
242    /*******************************  OLD:  *****************************/
243    
244  #define BINTRANS_DONT_RUN_NEXT          0x1000000  #define BINTRANS_DONT_RUN_NEXT          0x1000000
245  #define BINTRANS_N_MASK                 0x0ffffff  #define BINTRANS_N_MASK                 0x0ffffff
246    
# Line 203  struct r4000_cache_line { Line 251  struct r4000_cache_line {
251    
252  /*  Virtual to host address translation tables:  */  /*  Virtual to host address translation tables:  */
253  struct vth32_table {  struct vth32_table {
254          void                    *haddr_entry[1024];          void                    *haddr_entry[1024 * 2];
255          uint32_t                paddr_entry[1024];          uint32_t                paddr_entry[1024];
256          uint32_t                *bintrans_chunks[1024];          uint32_t                *bintrans_chunks[1024];
257          struct vth32_table      *next_free;          struct vth32_table      *next_free;
258          int                     refcount;          int                     refcount;
259  };  };
260    
261    /********************************************************************/
262    
263  struct mips_cpu {  struct mips_cpu {
264          struct mips_cpu_type_def cpu_type;          struct mips_cpu_type_def cpu_type;
265    
# Line 259  struct mips_cpu { Line 309  struct mips_cpu {
309          uint64_t        pc_last_physical_page;          uint64_t        pc_last_physical_page;
310          unsigned char   *pc_last_host_4k_page;          unsigned char   *pc_last_host_4k_page;
311    
312  #ifdef BINTRANS          /*  MIPS Bintrans:  */
313          int             dont_run_next_bintrans;          int             dont_run_next_bintrans;
314          int             bintrans_instructions_executed;  /*  set to the          int             bintrans_instructions_executed;  /*  set to the
315                                  number of bintranslated instructions executed                                  number of bintranslated instructions executed
# Line 282  struct mips_cpu { Line 332  struct mips_cpu {
332          struct vth32_table **vaddr_to_hostaddr_table0;  /*  should point to kernel or user  */          struct vth32_table **vaddr_to_hostaddr_table0;  /*  should point to kernel or user  */
333          struct vth32_table *next_free_vth_table;          struct vth32_table *next_free_vth_table;
334    
335    /*  Testing...  */
336            unsigned char   **host_OLD_load;
337            unsigned char   **host_OLD_store;
338            unsigned char   **host_load_orig;
339            unsigned char   **host_store_orig;
340            unsigned char   **huge_r2k3k_cache_table;
341    
342          /*  For 64-bit (generic) emulation:  */          /*  For 64-bit (generic) emulation:  */
343          unsigned char   *(*fast_vaddr_to_hostaddr)(struct cpu *cpu,          unsigned char   *(*fast_vaddr_to_hostaddr)(struct cpu *cpu,
344                              uint64_t vaddr, int writeflag);                              uint64_t vaddr, int writeflag);
# Line 290  struct mips_cpu { Line 347  struct mips_cpu {
347          uint64_t        bintrans_data_vaddr[N_BINTRANS_VADDR_TO_HOST];          uint64_t        bintrans_data_vaddr[N_BINTRANS_VADDR_TO_HOST];
348          unsigned char   *bintrans_data_hostpage[N_BINTRANS_VADDR_TO_HOST];          unsigned char   *bintrans_data_hostpage[N_BINTRANS_VADDR_TO_HOST];
349    
350          void            (*bintrans_loadstore_32bit)(struct cpu *);      /*  Note: incorrect args  */          void            (*bintrans_load_32bit)(struct cpu *);   /*  Note: incorrect args  */
351            void            (*bintrans_store_32bit)(struct cpu *);  /*  Note: incorrect args  */
352          void            (*bintrans_jump_to_32bit_pc)(struct cpu *);          void            (*bintrans_jump_to_32bit_pc)(struct cpu *);
353          void            (*bintrans_simple_exception)(struct cpu *, int);          void            (*bintrans_simple_exception)(struct cpu *, int);
354          void            (*bintrans_fast_rfe)(struct cpu *);          void            (*bintrans_fast_rfe)(struct cpu *);
355          void            (*bintrans_fast_eret)(struct cpu *);          void            (*bintrans_fast_eret)(struct cpu *);
356          void            (*bintrans_fast_tlbwri)(struct cpu *, int);          void            (*bintrans_fast_tlbwri)(struct cpu *, int);
357          void            (*bintrans_fast_tlbpr)(struct cpu *, int);          void            (*bintrans_fast_tlbpr)(struct cpu *, int);
 #endif  
358    
359  #ifdef ENABLE_MIPS16  #ifdef ENABLE_MIPS16
360          int             mips16;                 /*  non-zero if MIPS16 code is allowed  */          int             mips16;                 /*  non-zero if MIPS16 code is allowed  */
# Line 308  struct mips_cpu { Line 365  struct mips_cpu {
365          int             instruction_delay;          int             instruction_delay;
366  #endif  #endif
367    
         int             trace_tree_depth;  
   
368          uint64_t        delay_jmpaddr;          /*  only used if delay_slot > 0  */          uint64_t        delay_jmpaddr;          /*  only used if delay_slot > 0  */
369          int             delay_slot;          int             delay_slot;
370          int             nullify_next;           /*  set to 1 if next instruction          int             nullify_next;           /*  set to 1 if next instruction
# Line 362  struct mips_cpu { Line 417  struct mips_cpu {
417          int             cache_linesize[2];          int             cache_linesize[2];
418          int             cache_mask[2];          int             cache_mask[2];
419          int             cache_miss_penalty[2];          int             cache_miss_penalty[2];
420    
421            /*  Other stuff:  */
422            uint64_t        cop0_config_select1;
423    
424    
425            /*  NEW DYNTRANS:  */
426    
427    
428            /*
429             *  Instruction translation cache and Virtual->Physical->Host
430             *  address translation:
431             */
432            DYNTRANS_ITC(mips)
433            VPH_TLBS(mips,MIPS)
434            VPH32(mips,MIPS,uint64_t,uint8_t)
435            VPH64(mips,MIPS,uint8_t)
436  };  };
437    
438    
439  /*  cpu_mips.c:  */  /*  cpu_mips.c:  */
 struct cpu *mips_cpu_new(struct memory *mem, struct machine *machine,  
         int cpu_id, char *cpu_type_name);  
440  void mips_cpu_show_full_statistics(struct machine *m);  void mips_cpu_show_full_statistics(struct machine *m);
441  void mips_cpu_tlbdump(struct machine *m, int x, int rawflag);  void mips_cpu_tlbdump(struct machine *m, int x, int rawflag);
442  void mips_cpu_register_match(struct machine *m, char *name,  void mips_cpu_register_match(struct machine *m, char *name,
# Line 393  void mips_coproc_tlb_set_entry(struct cp Line 462  void mips_coproc_tlb_set_entry(struct cp
462          uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,          uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,
463          int valid0, int valid1, int dirty0, int dirty1, int global, int asid,          int valid0, int valid1, int dirty0, int dirty1, int global, int asid,
464          int cachealgo0, int cachealgo1);          int cachealgo0, int cachealgo1);
465  void update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void mips_OLD_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
466          unsigned char *host_page, int writeflag, uint64_t paddr_page);          unsigned char *host_page, int writeflag, uint64_t paddr_page);
467  void clear_all_chunks_from_all_tables(struct cpu *cpu);  void clear_all_chunks_from_all_tables(struct cpu *cpu);
468  void mips_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t paddr);  void mips_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int);
469  void coproc_register_read(struct cpu *cpu,  void coproc_register_read(struct cpu *cpu,
470          struct mips_coproc *cp, int reg_nr, uint64_t *ptr);          struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select);
471  void coproc_register_write(struct cpu *cpu,  void coproc_register_write(struct cpu *cpu,
472          struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int flag64);          struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int flag64,
473            int select);
474  void coproc_tlbpr(struct cpu *cpu, int readflag);  void coproc_tlbpr(struct cpu *cpu, int readflag);
475  void coproc_tlbwri(struct cpu *cpu, int randomflag);  void coproc_tlbwri(struct cpu *cpu, int randomflag);
476  void coproc_rfe(struct cpu *cpu);  void coproc_rfe(struct cpu *cpu);
# Line 420  int mips_memory_rw(struct cpu *cpu, stru Line 490  int mips_memory_rw(struct cpu *cpu, stru
490  int mips16_to_32(struct cpu *cpu, unsigned char *instr16, unsigned char *instr);  int mips16_to_32(struct cpu *cpu, unsigned char *instr16, unsigned char *instr);
491    
492    
493    /*  NEW DYNTRANS:  */
494    void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
495            unsigned char *host_page, int writeflag, uint64_t paddr_page);
496    void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
497    void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
498    
499    
500  #endif  /*  CPU_MIPS_H  */  #endif  /*  CPU_MIPS_H  */
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