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#define CPU_MIPS_H |
#define CPU_MIPS_H |
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/* |
/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_mips.h,v 1.16 2005/06/26 22:23:43 debug Exp $ |
* $Id: cpu_mips.h,v 1.26 2006/02/13 04:23:25 debug Exp $ |
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*/ |
*/ |
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#include "misc.h" |
#include "misc.h" |
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char isa_level; /* 1, 2, 3, 4, 5, 32, 64 */ |
char isa_level; /* 1, 2, 3, 4, 5, 32, 64 */ |
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int nr_of_tlb_entries; /* 32, 48, 64, ... */ |
int nr_of_tlb_entries; /* 32, 48, 64, ... */ |
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char instrs_per_cycle; /* simplified, 1, 2, or 4 */ |
char instrs_per_cycle; /* simplified, 1, 2, or 4 */ |
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int default_picache; |
int picache; |
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int default_pdcache; |
int pilinesize; |
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int default_pilinesize; |
int piways; |
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int default_pdlinesize; |
int pdcache; |
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int default_scache; |
int pdlinesize; |
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int default_slinesize; |
int pdways; |
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int scache; |
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int slinesize; |
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int sways; |
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}; |
}; |
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#define INITIAL_PC 0xffffffffbfc00000ULL |
#define INITIAL_PC 0xffffffffbfc00000ULL |
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#define MIPS_GPR_RA 31 /* ra */ |
#define MIPS_GPR_RA 31 /* ra */ |
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/* Meaning of delay_slot: */ |
/* Meaning of delay_slot: */ |
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#define NOT_DELAYED 0 |
#define NOT_DELAYED 0 |
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#define DELAYED 1 |
#define DELAYED 1 |
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#define TO_BE_DELAYED 2 |
#define TO_BE_DELAYED 2 |
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#define EXCEPTION_IN_DELAY_SLOT 0x100 |
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#define N_HI6 64 |
#define N_HI6 64 |
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#define N_SPECIAL 64 |
#define N_SPECIAL 64 |
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#define N_REGIMM 32 |
#define N_REGIMM 32 |
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/******************************* OLD: *****************************/ |
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/* Number of "tiny" translation cache entries: */ |
/* Number of "tiny" translation cache entries: */ |
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#define N_TRANSLATION_CACHE_INSTR 5 |
#define N_TRANSLATION_CACHE_INSTR 5 |
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#define N_TRANSLATION_CACHE_DATA 5 |
#define N_TRANSLATION_CACHE_DATA 5 |
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char dummy; |
char dummy; |
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}; |
}; |
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/********************************************************************/ |
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#ifdef ONEKPAGE |
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#define MIPS_IC_ENTRIES_SHIFT 8 |
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#else |
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#define MIPS_IC_ENTRIES_SHIFT 10 |
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#endif |
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#define MIPS_N_IC_ARGS 3 |
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#define MIPS_INSTR_ALIGNMENT_SHIFT 2 |
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#define MIPS_IC_ENTRIES_PER_PAGE (1 << MIPS_IC_ENTRIES_SHIFT) |
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#define MIPS_PC_TO_IC_ENTRY(a) (((a)>>MIPS_INSTR_ALIGNMENT_SHIFT) \ |
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& (MIPS_IC_ENTRIES_PER_PAGE-1)) |
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#define MIPS_ADDR_TO_PAGENR(a) ((a) >> (MIPS_IC_ENTRIES_SHIFT \ |
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+ MIPS_INSTR_ALIGNMENT_SHIFT)) |
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struct mips_instr_call { |
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void (*f)(struct cpu *, struct mips_instr_call *); |
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size_t arg[MIPS_N_IC_ARGS]; |
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}; |
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/* Translation cache struct for each physical page: */ |
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struct mips_tc_physpage { |
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struct mips_instr_call ics[MIPS_IC_ENTRIES_PER_PAGE + 3]; |
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uint32_t next_ofs; /* or 0 for end of chain */ |
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int flags; |
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uint64_t physaddr; |
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}; |
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#define MIPS_MAX_VPH_TLB_ENTRIES 128 |
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struct mips_vpg_tlb_entry { |
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uint8_t valid; |
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uint8_t writeflag; |
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unsigned char *host_page; |
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int64_t timestamp; |
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uint64_t vaddr_page; |
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uint64_t paddr_page; |
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}; |
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/******************************* OLD: *****************************/ |
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#define BINTRANS_DONT_RUN_NEXT 0x1000000 |
#define BINTRANS_DONT_RUN_NEXT 0x1000000 |
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#define BINTRANS_N_MASK 0x0ffffff |
#define BINTRANS_N_MASK 0x0ffffff |
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int refcount; |
int refcount; |
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}; |
}; |
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/********************************************************************/ |
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struct mips_cpu { |
struct mips_cpu { |
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struct mips_cpu_type_def cpu_type; |
struct mips_cpu_type_def cpu_type; |
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uint64_t pc_last_physical_page; |
uint64_t pc_last_physical_page; |
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unsigned char *pc_last_host_4k_page; |
unsigned char *pc_last_host_4k_page; |
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#ifdef BINTRANS |
/* MIPS Bintrans: */ |
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int dont_run_next_bintrans; |
int dont_run_next_bintrans; |
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int bintrans_instructions_executed; /* set to the |
int bintrans_instructions_executed; /* set to the |
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number of bintranslated instructions executed |
number of bintranslated instructions executed |
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struct vth32_table **vaddr_to_hostaddr_table0; /* should point to kernel or user */ |
struct vth32_table **vaddr_to_hostaddr_table0; /* should point to kernel or user */ |
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struct vth32_table *next_free_vth_table; |
struct vth32_table *next_free_vth_table; |
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/* Testing... */ |
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unsigned char **host_OLD_load; |
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unsigned char **host_OLD_store; |
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unsigned char **host_load_orig; |
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unsigned char **host_store_orig; |
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unsigned char **huge_r2k3k_cache_table; |
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/* For 64-bit (generic) emulation: */ |
/* For 64-bit (generic) emulation: */ |
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unsigned char *(*fast_vaddr_to_hostaddr)(struct cpu *cpu, |
unsigned char *(*fast_vaddr_to_hostaddr)(struct cpu *cpu, |
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uint64_t vaddr, int writeflag); |
uint64_t vaddr, int writeflag); |
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void (*bintrans_fast_eret)(struct cpu *); |
void (*bintrans_fast_eret)(struct cpu *); |
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void (*bintrans_fast_tlbwri)(struct cpu *, int); |
void (*bintrans_fast_tlbwri)(struct cpu *, int); |
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void (*bintrans_fast_tlbpr)(struct cpu *, int); |
void (*bintrans_fast_tlbpr)(struct cpu *, int); |
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#endif |
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#ifdef ENABLE_MIPS16 |
#ifdef ENABLE_MIPS16 |
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int mips16; /* non-zero if MIPS16 code is allowed */ |
int mips16; /* non-zero if MIPS16 code is allowed */ |
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int instruction_delay; |
int instruction_delay; |
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#endif |
#endif |
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int trace_tree_depth; |
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uint64_t delay_jmpaddr; /* only used if delay_slot > 0 */ |
uint64_t delay_jmpaddr; /* only used if delay_slot > 0 */ |
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int delay_slot; |
int delay_slot; |
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int nullify_next; /* set to 1 if next instruction |
int nullify_next; /* set to 1 if next instruction |
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/* Other stuff: */ |
/* Other stuff: */ |
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uint64_t cop0_config_select1; |
uint64_t cop0_config_select1; |
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/* NEW DYNTRANS: */ |
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/* |
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* Instruction translation cache and Virtual->Physical->Host |
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* address translation: |
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*/ |
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DYNTRANS_ITC(mips) |
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VPH_TLBS(mips,MIPS) |
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VPH32(mips,MIPS,uint64_t,uint8_t) |
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VPH64(mips,MIPS,uint8_t) |
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}; |
}; |
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uint64_t vaddr, uint64_t paddr0, uint64_t paddr1, |
uint64_t vaddr, uint64_t paddr0, uint64_t paddr1, |
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int valid0, int valid1, int dirty0, int dirty1, int global, int asid, |
int valid0, int valid1, int dirty0, int dirty1, int global, int asid, |
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int cachealgo0, int cachealgo1); |
int cachealgo0, int cachealgo1); |
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void update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
void mips_OLD_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void clear_all_chunks_from_all_tables(struct cpu *cpu); |
void clear_all_chunks_from_all_tables(struct cpu *cpu); |
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void mips_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t paddr); |
void mips_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int); |
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void coproc_register_read(struct cpu *cpu, |
void coproc_register_read(struct cpu *cpu, |
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struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select); |
struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select); |
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void coproc_register_write(struct cpu *cpu, |
void coproc_register_write(struct cpu *cpu, |
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int mips16_to_32(struct cpu *cpu, unsigned char *instr16, unsigned char *instr); |
int mips16_to_32(struct cpu *cpu, unsigned char *instr16, unsigned char *instr); |
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/* NEW DYNTRANS: */ |
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void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
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void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
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#endif /* CPU_MIPS_H */ |
#endif /* CPU_MIPS_H */ |