--- trunk/src/include/cpu_mips.h 2007/10/08 16:19:37 22 +++ trunk/src/include/cpu_mips.h 2007/10/08 16:20:26 28 @@ -28,17 +28,11 @@ * SUCH DAMAGE. * * - * $Id: cpu_mips.h,v 1.26 2006/02/13 04:23:25 debug Exp $ + * $Id: cpu_mips.h,v 1.45 2006/07/16 13:32:27 debug Exp $ */ #include "misc.h" -/* - * ENABLE_MIPS16 should be defined on the cc commandline using -D, if you - * want it. (This is done by ./configure --mips16) - */ -/* #define MFHILO_DELAY */ - struct cpu_family; struct emul; struct machine; @@ -55,6 +49,7 @@ char exc_model; /* EXC3K or EXC4K */ char mmu_model; /* MMU3K or MMU4K */ char isa_level; /* 1, 2, 3, 4, 5, 32, 64 */ + char isa_revision; /* 1 or 2 (for MIPS32/64) */ int nr_of_tlb_entries; /* 32, 48, 64, ... */ char instrs_per_cycle; /* simplified, 1, 2, or 4 */ int picache; @@ -74,6 +69,9 @@ /* * Coproc 0: + * + * NOTE: + * On R3000, only hi and lo0 are used, and then only the lowest 32 bits. */ #define N_MIPS_COPROC_REGS 32 struct mips_tlb { @@ -87,7 +85,13 @@ /* * Coproc 1: */ -#define N_MIPS_FCRS 32 +/* FPU control registers: */ +#define N_MIPS_FCRS 32 +#define MIPS_FPU_FCIR 0 +#define MIPS_FPU_FCCR 25 +#define MIPS_FPU_FCSR 31 +#define MIPS_FCSR_FCC0_SHIFT 23 +#define MIPS_FCSR_FCC1_SHIFT 25 struct mips_coproc { int coproc_nr; @@ -156,32 +160,12 @@ #define MIPS_GPR_FP 30 /* fp */ #define MIPS_GPR_RA 31 /* ra */ -/* Meaning of delay_slot: */ -#define NOT_DELAYED 0 -#define DELAYED 1 -#define TO_BE_DELAYED 2 -#define EXCEPTION_IN_DELAY_SLOT 0x100 - #define N_HI6 64 #define N_SPECIAL 64 #define N_REGIMM 32 /******************************* OLD: *****************************/ -/* Number of "tiny" translation cache entries: */ -#define N_TRANSLATION_CACHE_INSTR 5 -#define N_TRANSLATION_CACHE_DATA 5 - -struct translation_cache_entry { - int wf; - uint64_t vaddr_pfn; - uint64_t paddr; -}; - -/* This should be a value which the program counter - can "never" have: */ -#define PC_LAST_PAGE_IMPOSSIBLE_VALUE 3 - /* An "impossible" paddr: */ #define IMPOSSIBLE_PADDR 0x1212343456566767ULL @@ -215,6 +199,14 @@ #define MIPS_ADDR_TO_PAGENR(a) ((a) >> (MIPS_IC_ENTRIES_SHIFT \ + MIPS_INSTR_ALIGNMENT_SHIFT)) +#define MIPS_L2N 17 +#define MIPS_L3N 18 + +#define MIPS_MAX_VPH_TLB_ENTRIES 128 +DYNTRANS_MISC_DECLARATIONS(mips,MIPS,uint64_t) +DYNTRANS_MISC64_DECLARATIONS(mips,MIPS,uint8_t) + +#if 0 struct mips_instr_call { void (*f)(struct cpu *, struct mips_instr_call *); size_t arg[MIPS_N_IC_ARGS]; @@ -228,7 +220,6 @@ uint64_t physaddr; }; -#define MIPS_MAX_VPH_TLB_ENTRIES 128 struct mips_vpg_tlb_entry { uint8_t valid; uint8_t writeflag; @@ -237,26 +228,7 @@ uint64_t vaddr_page; uint64_t paddr_page; }; - - -/******************************* OLD: *****************************/ - -#define BINTRANS_DONT_RUN_NEXT 0x1000000 -#define BINTRANS_N_MASK 0x0ffffff - -#define N_SAFE_BINTRANS_LIMIT_SHIFT 14 -#define N_SAFE_BINTRANS_LIMIT ((1 << (N_SAFE_BINTRANS_LIMIT_SHIFT - 1)) - 1) - -#define N_BINTRANS_VADDR_TO_HOST 20 - -/* Virtual to host address translation tables: */ -struct vth32_table { - void *haddr_entry[1024 * 2]; - uint32_t paddr_entry[1024]; - uint32_t *bintrans_chunks[1024]; - struct vth32_table *next_free; - int refcount; -}; +#endif /********************************************************************/ @@ -268,147 +240,46 @@ int compare_register_set; /* Special purpose registers: */ - uint64_t pc_last; /* PC of last instruction */ uint64_t hi; uint64_t lo; + /* Dummy destination register when writing to the zero register: */ + uint64_t scratch; + /* General purpose registers: */ uint64_t gpr[N_MIPS_GPRS]; - /* - * The translation_cached stuff is used to speed up the - * most recent lookups into the TLB. Whenever the TLB is - * written to, translation_cached[] must be filled with zeros. - */ -#ifdef USE_TINY_CACHE - struct translation_cache_entry - translation_cache_instr[N_TRANSLATION_CACHE_INSTR]; - struct translation_cache_entry - translation_cache_data[N_TRANSLATION_CACHE_DATA]; -#endif - - /* - * For faster memory lookup when running instructions: - * - * Reading memory to load instructions is a very common thing in the - * emulator, and an instruction is very often read from the address - * following the previously executed instruction. That means that we - * don't have to go through the TLB each time. - * - * We then get the vaddr -> paddr translation for free. There is an - * even better case when the paddr is a RAM address (as opposed to an - * address in a memory mapped device). Then we can figure out the - * address in the host's memory directly, and skip the paddr -> host - * address calculation as well. - * - * A modification to the TLB should set the virtual_page variable to - * an "impossible" value, so that there won't be a hit on the next - * instruction. - */ - uint64_t pc_last_virtual_page; - uint64_t pc_last_physical_page; - unsigned char *pc_last_host_4k_page; - - /* MIPS Bintrans: */ - int dont_run_next_bintrans; - int bintrans_instructions_executed; /* set to the - number of bintranslated instructions executed - when running a bintrans codechunk */ - int pc_bintrans_paddr_valid; - uint64_t pc_bintrans_paddr; - unsigned char *pc_bintrans_host_4kpage; - - /* Chunk base address: */ - unsigned char *chunk_base_address; - - /* This should work for 32-bit MIPS emulation: */ - struct vth32_table *vaddr_to_hostaddr_nulltable; - struct vth32_table *vaddr_to_hostaddr_r2k3k_icachetable; - struct vth32_table *vaddr_to_hostaddr_r2k3k_dcachetable; - struct vth32_table **vaddr_to_hostaddr_table0_kernel; - struct vth32_table **vaddr_to_hostaddr_table0_cacheisol_i; - struct vth32_table **vaddr_to_hostaddr_table0_cacheisol_d; - struct vth32_table **vaddr_to_hostaddr_table0_user; - struct vth32_table **vaddr_to_hostaddr_table0; /* should point to kernel or user */ - struct vth32_table *next_free_vth_table; - -/* Testing... */ - unsigned char **host_OLD_load; - unsigned char **host_OLD_store; - unsigned char **host_load_orig; - unsigned char **host_store_orig; - unsigned char **huge_r2k3k_cache_table; - - /* For 64-bit (generic) emulation: */ - unsigned char *(*fast_vaddr_to_hostaddr)(struct cpu *cpu, - uint64_t vaddr, int writeflag); - int bintrans_next_index; - int bintrans_data_writable[N_BINTRANS_VADDR_TO_HOST]; - uint64_t bintrans_data_vaddr[N_BINTRANS_VADDR_TO_HOST]; - unsigned char *bintrans_data_hostpage[N_BINTRANS_VADDR_TO_HOST]; - - void (*bintrans_load_32bit)(struct cpu *); /* Note: incorrect args */ - void (*bintrans_store_32bit)(struct cpu *); /* Note: incorrect args */ - void (*bintrans_jump_to_32bit_pc)(struct cpu *); - void (*bintrans_simple_exception)(struct cpu *, int); - void (*bintrans_fast_rfe)(struct cpu *); - void (*bintrans_fast_eret)(struct cpu *); - void (*bintrans_fast_tlbwri)(struct cpu *, int); - void (*bintrans_fast_tlbpr)(struct cpu *, int); - -#ifdef ENABLE_MIPS16 - int mips16; /* non-zero if MIPS16 code is allowed */ - uint16_t mips16_extend; /* set on 'extend' instructions to the entire 16-bit extend instruction */ -#endif - -#ifdef ENABLE_INSTRUCTION_DELAYS - int instruction_delay; -#endif - - uint64_t delay_jmpaddr; /* only used if delay_slot > 0 */ - int delay_slot; int nullify_next; /* set to 1 if next instruction is to be nullified */ - /* This is set to non-zero, if it is possible at all that an - interrupt will occur. */ - int cached_interrupt_is_possible; - int show_trace_delay; /* 0=normal, > 0 = delay until show_trace */ uint64_t show_trace_addr; int last_was_jumptoself; int jump_to_self_reg; -#ifdef MFHILO_DELAY - int mfhi_delay; /* instructions since last mfhi */ - int mflo_delay; /* instructions since last mflo */ -#endif - int rmw; /* Read-Modify-Write */ int rmw_len; /* Length of rmw modification */ uint64_t rmw_addr; /* Address of rmw modification */ /* - * TODO: The R5900 has 128-bit registers. I'm not really sure + * NOTE: The R5900 has 128-bit registers. I'm not really sure * whether they are used a lot or not, at least with code produced * with gcc they are not. An important case however is lq and sq * (load and store of 128-bit values). These "upper halves" of R5900 * quadwords can be used in those cases. * + * hi1 and lo1 are the high 64-bit parts of the hi and lo registers. + * sa is a 32-bit "shift amount" register. + * * TODO: Generalize this. */ uint64_t gpr_quadhi[N_MIPS_GPRS]; + uint64_t hi1; + uint64_t lo1; + uint32_t r5900_sa; - /* - * Statistics: - */ - long stats_opcode[N_HI6]; - long stats__special[N_SPECIAL]; - long stats__regimm[N_REGIMM]; - long stats__special2[N_SPECIAL]; - /* Data and Instruction caches: */ unsigned char *cache[2]; void *cache_tags[2]; @@ -437,19 +308,18 @@ /* cpu_mips.c: */ -void mips_cpu_show_full_statistics(struct machine *m); +int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib); void mips_cpu_tlbdump(struct machine *m, int x, int rawflag); void mips_cpu_register_match(struct machine *m, char *name, int writeflag, uint64_t *valuep, int *match_register); void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs); int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, - int running, uint64_t addr, int bintrans); + int running, uint64_t addr); int mips_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr); int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr); void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr, /* uint64_t pagemask, */ int coproc_nr, uint64_t vaddr_vpn2, int vaddr_asid, int x_64); -void mips_cpu_cause_simple_exception(struct cpu *cpu, int exc_code); int mips_cpu_run(struct emul *emul, struct machine *machine); void mips_cpu_dumpinfo(struct cpu *cpu); void mips_cpu_list_available_types(void); @@ -462,10 +332,6 @@ uint64_t vaddr, uint64_t paddr0, uint64_t paddr1, int valid0, int valid1, int dirty0, int dirty1, int global, int asid, int cachealgo0, int cachealgo1); -void mips_OLD_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, - unsigned char *host_page, int writeflag, uint64_t paddr_page); -void clear_all_chunks_from_all_tables(struct cpu *cpu); -void mips_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int); void coproc_register_read(struct cpu *cpu, struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select); void coproc_register_write(struct cpu *cpu, @@ -485,16 +351,33 @@ int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags); +int translate_v2p_mmu3k(struct cpu *cpu, uint64_t vaddr, + uint64_t *return_addr, int flags); +int translate_v2p_mmu8k(struct cpu *cpu, uint64_t vaddr, + uint64_t *return_addr, int flags); +int translate_v2p_mmu10k(struct cpu *cpu, uint64_t vaddr, + uint64_t *return_addr, int flags); +int translate_v2p_mmu4100(struct cpu *cpu, uint64_t vaddr, + uint64_t *return_addr, int flags); +int translate_v2p_generic(struct cpu *cpu, uint64_t vaddr, + uint64_t *return_addr, int flags); + + +/* Dyntrans unaligned load/store: */ +void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic, + int is_left, int wlen, int store); -/* mips16.c: */ -int mips16_to_32(struct cpu *cpu, unsigned char *instr16, unsigned char *instr); - -/* NEW DYNTRANS: */ +int mips_run_instr(struct cpu *cpu); void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page); void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int); +int mips32_run_instr(struct cpu *cpu); +void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, + unsigned char *host_page, int writeflag, uint64_t paddr_page); +void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); +void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int); #endif /* CPU_MIPS_H */