src/include/cpu_mips.h

#ifndef CPU_MIPS_H
#define CPU_MIPS_H

/*
 *  Copyright (C) 2003-2006  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_mips.h,v 1.45 2006/07/16 13:32:27 debug Exp $
 */

#include "misc.h"

struct cpu_family;
struct emul;
struct machine;

/*
 *  CPU type definitions:  See mips_cpu_types.h.
 */

struct mips_cpu_type_def {
        char            *name;
        int             rev;
        int             sub;
        char            flags;
        char            exc_model;              /*  EXC3K or EXC4K  */
        char            mmu_model;              /*  MMU3K or MMU4K  */
        char            isa_level;              /*  1, 2, 3, 4, 5, 32, 64  */
        char            isa_revision;           /*  1 or 2 (for MIPS32/64)  */
        int             nr_of_tlb_entries;      /*  32, 48, 64, ...  */
        char            instrs_per_cycle;       /*  simplified, 1, 2, or 4  */
        int             picache;
        int             pilinesize;
        int             piways;
        int             pdcache;
        int             pdlinesize;
        int             pdways;
        int             scache;
        int             slinesize;
        int             sways;
};

#define INITIAL_PC                      0xffffffffbfc00000ULL
#define INITIAL_STACK_POINTER           (0xffffffffa0008000ULL - 256)


/*
 *  Coproc 0:
 *
 *  NOTE:
 *      On R3000, only hi and lo0 are used, and then only the lowest 32 bits.
 */
#define N_MIPS_COPROC_REGS      32
struct mips_tlb {
        uint64_t        hi;
        uint64_t        lo0;
        uint64_t        lo1;
        uint64_t        mask;
};


/*
 *  Coproc 1:
 */
/*  FPU control registers:  */
#define N_MIPS_FCRS                     32
#define MIPS_FPU_FCIR                   0
#define MIPS_FPU_FCCR                   25
#define MIPS_FPU_FCSR                   31
#define    MIPS_FCSR_FCC0_SHIFT            23
#define    MIPS_FCSR_FCC1_SHIFT            25

struct mips_coproc {
        int             coproc_nr;
        uint64_t        reg[N_MIPS_COPROC_REGS];

        /*  Only for COP0:  */
        struct mips_tlb *tlbs;
        int             nr_of_tlbs;

        /*  Only for COP1:  floating point control registers  */
        /*  (Maybe also for COP0?)  */
        uint64_t        fcr[N_MIPS_FCRS];
};

#define N_MIPS_COPROCS          4

#define N_MIPS_GPRS             32      /*  General purpose registers  */
#define N_MIPS_FPRS             32      /*  Floating point registers  */

/*
 *  These should all be 2 characters wide:
 *
 *  NOTE: These are for 32-bit ABIs. For the 64-bit ABI, registers 8..11
 *  are used to pass arguments and are then called "a4".."a7".
 *
 *  TODO: Should there be two different variants of this? It's not really
 *  possible to figure out in some easy way if the code running was
 *  written for a 32-bit or 64-bit ABI.
 */
#define MIPS_REGISTER_NAMES     { \
        "zr", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
        "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
        "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
        "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra"  }

#define MIPS_GPR_ZERO           0               /*  zero  */
#define MIPS_GPR_AT             1               /*  at  */
#define MIPS_GPR_V0             2               /*  v0  */
#define MIPS_GPR_V1             3               /*  v1  */
#define MIPS_GPR_A0             4               /*  a0  */
#define MIPS_GPR_A1             5               /*  a1  */
#define MIPS_GPR_A2             6               /*  a2  */
#define MIPS_GPR_A3             7               /*  a3  */
#define MIPS_GPR_T0             8               /*  t0  */
#define MIPS_GPR_T1             9               /*  t1  */
#define MIPS_GPR_T2             10              /*  t2  */
#define MIPS_GPR_T3             11              /*  t3  */
#define MIPS_GPR_T4             12              /*  t4  */
#define MIPS_GPR_T5             13              /*  t5  */
#define MIPS_GPR_T6             14              /*  t6  */
#define MIPS_GPR_T7             15              /*  t7  */
#define MIPS_GPR_S0             16              /*  s0  */
#define MIPS_GPR_S1             17              /*  s1  */
#define MIPS_GPR_S2             18              /*  s2  */
#define MIPS_GPR_S3             19              /*  s3  */
#define MIPS_GPR_S4             20              /*  s4  */
#define MIPS_GPR_S5             21              /*  s5  */
#define MIPS_GPR_S6             22              /*  s6  */
#define MIPS_GPR_S7             23              /*  s7  */
#define MIPS_GPR_T8             24              /*  t8  */
#define MIPS_GPR_T9             25              /*  t9  */
#define MIPS_GPR_K0             26              /*  k0  */
#define MIPS_GPR_K1             27              /*  k1  */
#define MIPS_GPR_GP             28              /*  gp  */
#define MIPS_GPR_SP             29              /*  sp  */
#define MIPS_GPR_FP             30              /*  fp  */
#define MIPS_GPR_RA             31              /*  ra  */

#define N_HI6                   64
#define N_SPECIAL               64
#define N_REGIMM                32

/*******************************  OLD:  *****************************/

/*  An "impossible" paddr:  */
#define IMPOSSIBLE_PADDR                0x1212343456566767ULL

#define DEFAULT_PCACHE_SIZE             15      /*  32 KB  */
#define DEFAULT_PCACHE_LINESIZE         5       /*  32 bytes  */

struct r3000_cache_line {
        uint32_t        tag_paddr;
        int             tag_valid;
};
#define R3000_TAG_VALID         1
#define R3000_TAG_DIRTY         2

struct r4000_cache_line {
        char            dummy;
};

/********************************************************************/

#ifdef ONEKPAGE
#define MIPS_IC_ENTRIES_SHIFT           8
#else
#define MIPS_IC_ENTRIES_SHIFT           10
#endif

#define MIPS_N_IC_ARGS                  3
#define MIPS_INSTR_ALIGNMENT_SHIFT      2
#define MIPS_IC_ENTRIES_PER_PAGE        (1 << MIPS_IC_ENTRIES_SHIFT)
#define MIPS_PC_TO_IC_ENTRY(a)          (((a)>>MIPS_INSTR_ALIGNMENT_SHIFT) \
                                        & (MIPS_IC_ENTRIES_PER_PAGE-1))
#define MIPS_ADDR_TO_PAGENR(a)          ((a) >> (MIPS_IC_ENTRIES_SHIFT \
                                        + MIPS_INSTR_ALIGNMENT_SHIFT))

#define MIPS_L2N                17
#define MIPS_L3N                18

#define MIPS_MAX_VPH_TLB_ENTRIES        128
DYNTRANS_MISC_DECLARATIONS(mips,MIPS,uint64_t)
DYNTRANS_MISC64_DECLARATIONS(mips,MIPS,uint8_t)

#if 0
struct mips_instr_call {
        void    (*f)(struct cpu *, struct mips_instr_call *);
        size_t  arg[MIPS_N_IC_ARGS];
};

/*  Translation cache struct for each physical page:  */
struct mips_tc_physpage {
        struct mips_instr_call ics[MIPS_IC_ENTRIES_PER_PAGE + 3];
        uint32_t        next_ofs;       /*  or 0 for end of chain  */
        int             flags;
        uint64_t        physaddr;
};

struct mips_vpg_tlb_entry {
        uint8_t         valid;
        uint8_t         writeflag;
        unsigned char   *host_page;
        int64_t         timestamp;
        uint64_t        vaddr_page;
        uint64_t        paddr_page;
};
#endif

/********************************************************************/

struct mips_cpu {
        struct mips_cpu_type_def cpu_type;

        struct mips_coproc *coproc[N_MIPS_COPROCS];

        int             compare_register_set;

        /*  Special purpose registers:  */
        uint64_t        hi;
        uint64_t        lo;

        /*  Dummy destination register when writing to the zero register:  */
        uint64_t        scratch;

        /*  General purpose registers:  */
        uint64_t        gpr[N_MIPS_GPRS];

        int             nullify_next;           /*  set to 1 if next instruction
                                                        is to be nullified  */

        int             show_trace_delay;       /*  0=normal, > 0 = delay until show_trace  */
        uint64_t        show_trace_addr;

        int             last_was_jumptoself;
        int             jump_to_self_reg;

        int             rmw;            /*  Read-Modify-Write  */
        int             rmw_len;        /*  Length of rmw modification  */
        uint64_t        rmw_addr;       /*  Address of rmw modification  */

        /*
         *  NOTE:  The R5900 has 128-bit registers. I'm not really sure
         *  whether they are used a lot or not, at least with code produced
         *  with gcc they are not. An important case however is lq and sq
         *  (load and store of 128-bit values). These "upper halves" of R5900
         *  quadwords can be used in those cases.
         *
         *  hi1 and lo1 are the high 64-bit parts of the hi and lo registers.
         *  sa is a 32-bit "shift amount" register.
         *
         *  TODO:  Generalize this.
         */
        uint64_t        gpr_quadhi[N_MIPS_GPRS];
        uint64_t        hi1;
        uint64_t        lo1;
        uint32_t        r5900_sa;


        /*  Data and Instruction caches:  */
        unsigned char   *cache[2];
        void            *cache_tags[2];
        uint64_t        cache_last_paddr[2];
        int             cache_size[2];
        int             cache_linesize[2];
        int             cache_mask[2];
        int             cache_miss_penalty[2];

        /*  Other stuff:  */
        uint64_t        cop0_config_select1;


        /*  NEW DYNTRANS:  */


        /*
         *  Instruction translation cache and Virtual->Physical->Host
         *  address translation:
         */
        DYNTRANS_ITC(mips)
        VPH_TLBS(mips,MIPS)
        VPH32(mips,MIPS,uint64_t,uint8_t)
        VPH64(mips,MIPS,uint8_t)
};


/*  cpu_mips.c:  */
int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
void mips_cpu_tlbdump(struct machine *m, int x, int rawflag);
void mips_cpu_register_match(struct machine *m, char *name, 
        int writeflag, uint64_t *valuep, int *match_register);
void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs);
int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
        int running, uint64_t addr);
int mips_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr);
int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr);
void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr,
        /*  uint64_t pagemask,  */  int coproc_nr, uint64_t vaddr_vpn2,
        int vaddr_asid, int x_64);
int mips_cpu_run(struct emul *emul, struct machine *machine);
void mips_cpu_dumpinfo(struct cpu *cpu);
void mips_cpu_list_available_types(void);
int mips_cpu_family_init(struct cpu_family *);


/*  cpu_mips_coproc.c:  */
struct mips_coproc *mips_coproc_new(struct cpu *cpu, int coproc_nr);
void mips_coproc_tlb_set_entry(struct cpu *cpu, int entrynr, int size,
        uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,
        int valid0, int valid1, int dirty0, int dirty1, int global, int asid,
        int cachealgo0, int cachealgo1);
void coproc_register_read(struct cpu *cpu,
        struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select);
void coproc_register_write(struct cpu *cpu,
        struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int flag64,
        int select);
void coproc_tlbpr(struct cpu *cpu, int readflag);
void coproc_tlbwri(struct cpu *cpu, int randomflag);
void coproc_rfe(struct cpu *cpu);
void coproc_eret(struct cpu *cpu);
void coproc_function(struct cpu *cpu, struct mips_coproc *cp, int cpnr,
        uint32_t function, int unassemble_only, int running);


/*  memory_mips.c:  */
int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr,
        int writeflag, size_t len, unsigned char *data);
int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
        unsigned char *data, size_t len, int writeflag, int cache_flags);

int translate_v2p_mmu3k(struct cpu *cpu, uint64_t vaddr,
        uint64_t *return_addr, int flags);
int translate_v2p_mmu8k(struct cpu *cpu, uint64_t vaddr,
        uint64_t *return_addr, int flags);
int translate_v2p_mmu10k(struct cpu *cpu, uint64_t vaddr,
        uint64_t *return_addr, int flags);
int translate_v2p_mmu4100(struct cpu *cpu, uint64_t vaddr,
        uint64_t *return_addr, int flags);
int translate_v2p_generic(struct cpu *cpu, uint64_t vaddr,
        uint64_t *return_addr, int flags);


/*  Dyntrans unaligned load/store:  */
void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic, 
        int is_left, int wlen, int store);


int mips_run_instr(struct cpu *cpu);
void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
int mips32_run_instr(struct cpu *cpu);
void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);


#endif  /*  CPU_MIPS_H  */
1	dpavlin	4	#ifndef CPU_MIPS_H
2			#define CPU_MIPS_H
3
4			/*
5	dpavlin	22	* Copyright (C) 2003-2006 Anders Gavare. All rights reserved.
6	dpavlin	4	*
7			* Redistribution and use in source and binary forms, with or without
8			* modification, are permitted provided that the following conditions are met:
9			*
10			* 1. Redistributions of source code must retain the above copyright
11			* notice, this list of conditions and the following disclaimer.
12			* 2. Redistributions in binary form must reproduce the above copyright
13			* notice, this list of conditions and the following disclaimer in the
14			* documentation and/or other materials provided with the distribution.
15			* 3. The name of the author may not be used to endorse or promote products
16			* derived from this software without specific prior written permission.
17			*
18			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28			* SUCH DAMAGE.
29			*
30			*
31	dpavlin	28	* $Id: cpu_mips.h,v 1.45 2006/07/16 13:32:27 debug Exp $
32	dpavlin	4	*/
33
34			#include "misc.h"
35
36			struct cpu_family;
37			struct emul;
38			struct machine;
39
40			/*
41			* CPU type definitions: See mips_cpu_types.h.
42			*/
43
44			struct mips_cpu_type_def {
45			char *name;
46			int rev;
47			int sub;
48			char flags;
49			char exc_model; /* EXC3K or EXC4K */
50			char mmu_model; /* MMU3K or MMU4K */
51			char isa_level; /* 1, 2, 3, 4, 5, 32, 64 */
52	dpavlin	24	char isa_revision; /* 1 or 2 (for MIPS32/64) */
53	dpavlin	4	int nr_of_tlb_entries; /* 32, 48, 64, ... */
54			char instrs_per_cycle; /* simplified, 1, 2, or 4 */
55	dpavlin	12	int picache;
56			int pilinesize;
57			int piways;
58			int pdcache;
59			int pdlinesize;
60			int pdways;
61			int scache;
62			int slinesize;
63			int sways;
64	dpavlin	4	};
65
66			#define INITIAL_PC 0xffffffffbfc00000ULL
67			#define INITIAL_STACK_POINTER (0xffffffffa0008000ULL - 256)
68
69
70			/*
71			* Coproc 0:
72	dpavlin	28	*
73			* NOTE:
74			* On R3000, only hi and lo0 are used, and then only the lowest 32 bits.
75	dpavlin	4	*/
76			#define N_MIPS_COPROC_REGS 32
77			struct mips_tlb {
78			uint64_t hi;
79			uint64_t lo0;
80			uint64_t lo1;
81			uint64_t mask;
82			};
83
84
85			/*
86			* Coproc 1:
87			*/
88	dpavlin	24	/* FPU control registers: */
89			#define N_MIPS_FCRS 32
90			#define MIPS_FPU_FCIR 0
91			#define MIPS_FPU_FCCR 25
92			#define MIPS_FPU_FCSR 31
93			#define MIPS_FCSR_FCC0_SHIFT 23
94			#define MIPS_FCSR_FCC1_SHIFT 25
95	dpavlin	4
96			struct mips_coproc {
97			int coproc_nr;
98			uint64_t reg[N_MIPS_COPROC_REGS];
99
100			/* Only for COP0: */
101			struct mips_tlb *tlbs;
102			int nr_of_tlbs;
103
104			/* Only for COP1: floating point control registers */
105			/* (Maybe also for COP0?) */
106			uint64_t fcr[N_MIPS_FCRS];
107			};
108
109			#define N_MIPS_COPROCS 4
110
111			#define N_MIPS_GPRS 32 /* General purpose registers */
112			#define N_MIPS_FPRS 32 /* Floating point registers */
113
114			/*
115			* These should all be 2 characters wide:
116			*
117			* NOTE: These are for 32-bit ABIs. For the 64-bit ABI, registers 8..11
118			* are used to pass arguments and are then called "a4".."a7".
119			*
120			* TODO: Should there be two different variants of this? It's not really
121			* possible to figure out in some easy way if the code running was
122			* written for a 32-bit or 64-bit ABI.
123			*/
124			#define MIPS_REGISTER_NAMES { \
125			"zr", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
126			"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
127			"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
128			"t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra" }
129
130			#define MIPS_GPR_ZERO 0 /* zero */
131			#define MIPS_GPR_AT 1 /* at */
132			#define MIPS_GPR_V0 2 /* v0 */
133			#define MIPS_GPR_V1 3 /* v1 */
134			#define MIPS_GPR_A0 4 /* a0 */
135			#define MIPS_GPR_A1 5 /* a1 */
136			#define MIPS_GPR_A2 6 /* a2 */
137			#define MIPS_GPR_A3 7 /* a3 */
138			#define MIPS_GPR_T0 8 /* t0 */
139			#define MIPS_GPR_T1 9 /* t1 */
140			#define MIPS_GPR_T2 10 /* t2 */
141			#define MIPS_GPR_T3 11 /* t3 */
142			#define MIPS_GPR_T4 12 /* t4 */
143			#define MIPS_GPR_T5 13 /* t5 */
144			#define MIPS_GPR_T6 14 /* t6 */
145			#define MIPS_GPR_T7 15 /* t7 */
146			#define MIPS_GPR_S0 16 /* s0 */
147			#define MIPS_GPR_S1 17 /* s1 */
148			#define MIPS_GPR_S2 18 /* s2 */
149			#define MIPS_GPR_S3 19 /* s3 */
150			#define MIPS_GPR_S4 20 /* s4 */
151			#define MIPS_GPR_S5 21 /* s5 */
152			#define MIPS_GPR_S6 22 /* s6 */
153			#define MIPS_GPR_S7 23 /* s7 */
154			#define MIPS_GPR_T8 24 /* t8 */
155			#define MIPS_GPR_T9 25 /* t9 */
156			#define MIPS_GPR_K0 26 /* k0 */
157			#define MIPS_GPR_K1 27 /* k1 */
158			#define MIPS_GPR_GP 28 /* gp */
159			#define MIPS_GPR_SP 29 /* sp */
160			#define MIPS_GPR_FP 30 /* fp */
161			#define MIPS_GPR_RA 31 /* ra */
162
163			#define N_HI6 64
164			#define N_SPECIAL 64
165			#define N_REGIMM 32
166
167	dpavlin	22	/***************************** OLD: ***************************/
168
169	dpavlin	4	/* An "impossible" paddr: */
170			#define IMPOSSIBLE_PADDR 0x1212343456566767ULL
171
172			#define DEFAULT_PCACHE_SIZE 15 /* 32 KB */
173			#define DEFAULT_PCACHE_LINESIZE 5 /* 32 bytes */
174
175			struct r3000_cache_line {
176			uint32_t tag_paddr;
177			int tag_valid;
178			};
179			#define R3000_TAG_VALID 1
180			#define R3000_TAG_DIRTY 2
181
182			struct r4000_cache_line {
183			char dummy;
184			};
185
186	dpavlin	22	/********************************************************************/
187
188			#ifdef ONEKPAGE
189			#define MIPS_IC_ENTRIES_SHIFT 8
190			#else
191			#define MIPS_IC_ENTRIES_SHIFT 10
192			#endif
193
194			#define MIPS_N_IC_ARGS 3
195			#define MIPS_INSTR_ALIGNMENT_SHIFT 2
196			#define MIPS_IC_ENTRIES_PER_PAGE (1 << MIPS_IC_ENTRIES_SHIFT)
197			#define MIPS_PC_TO_IC_ENTRY(a) (((a)>>MIPS_INSTR_ALIGNMENT_SHIFT) \
198			& (MIPS_IC_ENTRIES_PER_PAGE-1))
199			#define MIPS_ADDR_TO_PAGENR(a) ((a) >> (MIPS_IC_ENTRIES_SHIFT \
200			+ MIPS_INSTR_ALIGNMENT_SHIFT))
201
202	dpavlin	24	#define MIPS_L2N 17
203			#define MIPS_L3N 18
204
205			#define MIPS_MAX_VPH_TLB_ENTRIES 128
206			DYNTRANS_MISC_DECLARATIONS(mips,MIPS,uint64_t)
207			DYNTRANS_MISC64_DECLARATIONS(mips,MIPS,uint8_t)
208
209			#if 0
210	dpavlin	22	struct mips_instr_call {
211			void (f)(struct cpu , struct mips_instr_call *);
212			size_t arg[MIPS_N_IC_ARGS];
213			};
214
215			/* Translation cache struct for each physical page: */
216			struct mips_tc_physpage {
217			struct mips_instr_call ics[MIPS_IC_ENTRIES_PER_PAGE + 3];
218			uint32_t next_ofs; /* or 0 for end of chain */
219			int flags;
220			uint64_t physaddr;
221			};
222
223			struct mips_vpg_tlb_entry {
224			uint8_t valid;
225			uint8_t writeflag;
226			unsigned char *host_page;
227			int64_t timestamp;
228			uint64_t vaddr_page;
229			uint64_t paddr_page;
230			};
231	dpavlin	24	#endif
232	dpavlin	22
233			/********************************************************************/
234
235	dpavlin	4	struct mips_cpu {
236			struct mips_cpu_type_def cpu_type;
237
238			struct mips_coproc *coproc[N_MIPS_COPROCS];
239
240			int compare_register_set;
241
242			/* Special purpose registers: */
243			uint64_t hi;
244			uint64_t lo;
245
246	dpavlin	24	/* Dummy destination register when writing to the zero register: */
247			uint64_t scratch;
248
249	dpavlin	4	/* General purpose registers: */
250			uint64_t gpr[N_MIPS_GPRS];
251
252			int nullify_next; /* set to 1 if next instruction
253			is to be nullified */
254
255			int show_trace_delay; /* 0=normal, > 0 = delay until show_trace */
256			uint64_t show_trace_addr;
257
258			int last_was_jumptoself;
259			int jump_to_self_reg;
260
261			int rmw; /* Read-Modify-Write */
262			int rmw_len; /* Length of rmw modification */
263			uint64_t rmw_addr; /* Address of rmw modification */
264
265			/*
266	dpavlin	24	* NOTE: The R5900 has 128-bit registers. I'm not really sure
267	dpavlin	4	* whether they are used a lot or not, at least with code produced
268			* with gcc they are not. An important case however is lq and sq
269			* (load and store of 128-bit values). These "upper halves" of R5900
270			* quadwords can be used in those cases.
271			*
272	dpavlin	24	* hi1 and lo1 are the high 64-bit parts of the hi and lo registers.
273			* sa is a 32-bit "shift amount" register.
274			*
275	dpavlin	4	* TODO: Generalize this.
276			*/
277			uint64_t gpr_quadhi[N_MIPS_GPRS];
278	dpavlin	24	uint64_t hi1;
279			uint64_t lo1;
280			uint32_t r5900_sa;
281	dpavlin	4
282
283			/* Data and Instruction caches: */
284			unsigned char *cache[2];
285			void *cache_tags[2];
286			uint64_t cache_last_paddr[2];
287			int cache_size[2];
288			int cache_linesize[2];
289			int cache_mask[2];
290			int cache_miss_penalty[2];
291	dpavlin	10
292			/* Other stuff: */
293			uint64_t cop0_config_select1;
294	dpavlin	22
295
296			/* NEW DYNTRANS: */
297
298
299			/*
300			* Instruction translation cache and Virtual->Physical->Host
301			* address translation:
302			*/
303			DYNTRANS_ITC(mips)
304			VPH_TLBS(mips,MIPS)
305			VPH32(mips,MIPS,uint64_t,uint8_t)
306			VPH64(mips,MIPS,uint8_t)
307	dpavlin	4	};
308
309
310			/* cpu_mips.c: */
311	dpavlin	24	int mips_cpu_instruction_has_delayslot(struct cpu cpu, unsigned char ib);
312	dpavlin	4	void mips_cpu_tlbdump(struct machine *m, int x, int rawflag);
313			void mips_cpu_register_match(struct machine m, char name,
314			int writeflag, uint64_t valuep, int match_register);
315			void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs);
316			int mips_cpu_disassemble_instr(struct cpu cpu, unsigned char instr,
317	dpavlin	24	int running, uint64_t addr);
318	dpavlin	4	int mips_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr);
319			int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr);
320			void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr,
321			/* uint64_t pagemask, */ int coproc_nr, uint64_t vaddr_vpn2,
322			int vaddr_asid, int x_64);
323			int mips_cpu_run(struct emul emul, struct machine machine);
324			void mips_cpu_dumpinfo(struct cpu *cpu);
325			void mips_cpu_list_available_types(void);
326			int mips_cpu_family_init(struct cpu_family *);
327
328
329			/* cpu_mips_coproc.c: */
330			struct mips_coproc mips_coproc_new(struct cpu cpu, int coproc_nr);
331			void mips_coproc_tlb_set_entry(struct cpu *cpu, int entrynr, int size,
332			uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,
333			int valid0, int valid1, int dirty0, int dirty1, int global, int asid,
334			int cachealgo0, int cachealgo1);
335			void coproc_register_read(struct cpu *cpu,
336	dpavlin	10	struct mips_coproc cp, int reg_nr, uint64_t ptr, int select);
337	dpavlin	4	void coproc_register_write(struct cpu *cpu,
338	dpavlin	10	struct mips_coproc cp, int reg_nr, uint64_t ptr, int flag64,
339			int select);
340	dpavlin	4	void coproc_tlbpr(struct cpu *cpu, int readflag);
341			void coproc_tlbwri(struct cpu *cpu, int randomflag);
342			void coproc_rfe(struct cpu *cpu);
343			void coproc_eret(struct cpu *cpu);
344			void coproc_function(struct cpu cpu, struct mips_coproc cp, int cpnr,
345			uint32_t function, int unassemble_only, int running);
346
347
348			/* memory_mips.c: */
349			int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr,
350			int writeflag, size_t len, unsigned char *data);
351			int mips_memory_rw(struct cpu cpu, struct memory mem, uint64_t vaddr,
352			unsigned char *data, size_t len, int writeflag, int cache_flags);
353
354	dpavlin	26	int translate_v2p_mmu3k(struct cpu *cpu, uint64_t vaddr,
355			uint64_t *return_addr, int flags);
356			int translate_v2p_mmu8k(struct cpu *cpu, uint64_t vaddr,
357			uint64_t *return_addr, int flags);
358			int translate_v2p_mmu10k(struct cpu *cpu, uint64_t vaddr,
359			uint64_t *return_addr, int flags);
360			int translate_v2p_mmu4100(struct cpu *cpu, uint64_t vaddr,
361			uint64_t *return_addr, int flags);
362			int translate_v2p_generic(struct cpu *cpu, uint64_t vaddr,
363			uint64_t *return_addr, int flags);
364	dpavlin	4
365	dpavlin	26
366	dpavlin	24	/* Dyntrans unaligned load/store: */
367			void mips_unaligned_loadstore(struct cpu cpu, struct mips_instr_call ic,
368			int is_left, int wlen, int store);
369	dpavlin	4
370
371	dpavlin	28	int mips_run_instr(struct cpu *cpu);
372	dpavlin	22	void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
373			unsigned char *host_page, int writeflag, uint64_t paddr_page);
374			void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
375			void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
376	dpavlin	28	int mips32_run_instr(struct cpu *cpu);
377	dpavlin	24	void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
378			unsigned char *host_page, int writeflag, uint64_t paddr_page);
379			void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
380			void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
381	dpavlin	22
382
383	dpavlin	4	#endif /* CPU_MIPS_H */