/[gxemul]/trunk/src/include/cpu_mips.h
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Revision 26 - (hide annotations)
Mon Oct 8 16:20:10 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 11842 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1264 2006/06/25 11:08:04 debug Exp $
20060624	Replacing the error-prone machine type initialization stuff
		with something more reasonable.
		Finally removing the old "cpu_run" kludge; moving around stuff
		in machine.c and emul.c to better suit the dyntrans system.
		Various minor dyntrans cleanups (renaming translate_address to
		translate_v2p, and experimenting with template physpages).
20060625	Removing the speed hack which separated the vph entries into
		two halves (code vs data); things seem a lot more stable now.
		Minor performance hack: R2000/R3000 cache isolation now only
		clears address translations when going into isolation, not
		when going out of it.
		Fixing the MIPS interrupt problems by letting mtc0 immediately
		cause interrupts.

==============  RELEASE 0.4.0.1  ==============


1 dpavlin 4 #ifndef CPU_MIPS_H
2     #define CPU_MIPS_H
3    
4     /*
5 dpavlin 22 * Copyright (C) 2003-2006 Anders Gavare. All rights reserved.
6 dpavlin 4 *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31 dpavlin 26 * $Id: cpu_mips.h,v 1.43 2006/06/24 21:47:24 debug Exp $
32 dpavlin 4 */
33    
34     #include "misc.h"
35    
36     struct cpu_family;
37     struct emul;
38     struct machine;
39    
40     /*
41     * CPU type definitions: See mips_cpu_types.h.
42     */
43    
44     struct mips_cpu_type_def {
45     char *name;
46     int rev;
47     int sub;
48     char flags;
49     char exc_model; /* EXC3K or EXC4K */
50     char mmu_model; /* MMU3K or MMU4K */
51     char isa_level; /* 1, 2, 3, 4, 5, 32, 64 */
52 dpavlin 24 char isa_revision; /* 1 or 2 (for MIPS32/64) */
53 dpavlin 4 int nr_of_tlb_entries; /* 32, 48, 64, ... */
54     char instrs_per_cycle; /* simplified, 1, 2, or 4 */
55 dpavlin 12 int picache;
56     int pilinesize;
57     int piways;
58     int pdcache;
59     int pdlinesize;
60     int pdways;
61     int scache;
62     int slinesize;
63     int sways;
64 dpavlin 4 };
65    
66     #define INITIAL_PC 0xffffffffbfc00000ULL
67     #define INITIAL_STACK_POINTER (0xffffffffa0008000ULL - 256)
68    
69    
70     /*
71     * Coproc 0:
72     */
73     #define N_MIPS_COPROC_REGS 32
74     struct mips_tlb {
75     uint64_t hi;
76     uint64_t lo0;
77     uint64_t lo1;
78     uint64_t mask;
79     };
80    
81    
82     /*
83     * Coproc 1:
84     */
85 dpavlin 24 /* FPU control registers: */
86     #define N_MIPS_FCRS 32
87     #define MIPS_FPU_FCIR 0
88     #define MIPS_FPU_FCCR 25
89     #define MIPS_FPU_FCSR 31
90     #define MIPS_FCSR_FCC0_SHIFT 23
91     #define MIPS_FCSR_FCC1_SHIFT 25
92 dpavlin 4
93     struct mips_coproc {
94     int coproc_nr;
95     uint64_t reg[N_MIPS_COPROC_REGS];
96    
97     /* Only for COP0: */
98     struct mips_tlb *tlbs;
99     int nr_of_tlbs;
100    
101     /* Only for COP1: floating point control registers */
102     /* (Maybe also for COP0?) */
103     uint64_t fcr[N_MIPS_FCRS];
104     };
105    
106     #define N_MIPS_COPROCS 4
107    
108     #define N_MIPS_GPRS 32 /* General purpose registers */
109     #define N_MIPS_FPRS 32 /* Floating point registers */
110    
111     /*
112     * These should all be 2 characters wide:
113     *
114     * NOTE: These are for 32-bit ABIs. For the 64-bit ABI, registers 8..11
115     * are used to pass arguments and are then called "a4".."a7".
116     *
117     * TODO: Should there be two different variants of this? It's not really
118     * possible to figure out in some easy way if the code running was
119     * written for a 32-bit or 64-bit ABI.
120     */
121     #define MIPS_REGISTER_NAMES { \
122     "zr", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
123     "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
124     "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
125     "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra" }
126    
127     #define MIPS_GPR_ZERO 0 /* zero */
128     #define MIPS_GPR_AT 1 /* at */
129     #define MIPS_GPR_V0 2 /* v0 */
130     #define MIPS_GPR_V1 3 /* v1 */
131     #define MIPS_GPR_A0 4 /* a0 */
132     #define MIPS_GPR_A1 5 /* a1 */
133     #define MIPS_GPR_A2 6 /* a2 */
134     #define MIPS_GPR_A3 7 /* a3 */
135     #define MIPS_GPR_T0 8 /* t0 */
136     #define MIPS_GPR_T1 9 /* t1 */
137     #define MIPS_GPR_T2 10 /* t2 */
138     #define MIPS_GPR_T3 11 /* t3 */
139     #define MIPS_GPR_T4 12 /* t4 */
140     #define MIPS_GPR_T5 13 /* t5 */
141     #define MIPS_GPR_T6 14 /* t6 */
142     #define MIPS_GPR_T7 15 /* t7 */
143     #define MIPS_GPR_S0 16 /* s0 */
144     #define MIPS_GPR_S1 17 /* s1 */
145     #define MIPS_GPR_S2 18 /* s2 */
146     #define MIPS_GPR_S3 19 /* s3 */
147     #define MIPS_GPR_S4 20 /* s4 */
148     #define MIPS_GPR_S5 21 /* s5 */
149     #define MIPS_GPR_S6 22 /* s6 */
150     #define MIPS_GPR_S7 23 /* s7 */
151     #define MIPS_GPR_T8 24 /* t8 */
152     #define MIPS_GPR_T9 25 /* t9 */
153     #define MIPS_GPR_K0 26 /* k0 */
154     #define MIPS_GPR_K1 27 /* k1 */
155     #define MIPS_GPR_GP 28 /* gp */
156     #define MIPS_GPR_SP 29 /* sp */
157     #define MIPS_GPR_FP 30 /* fp */
158     #define MIPS_GPR_RA 31 /* ra */
159    
160     #define N_HI6 64
161     #define N_SPECIAL 64
162     #define N_REGIMM 32
163    
164 dpavlin 22 /******************************* OLD: *****************************/
165    
166 dpavlin 4 /* An "impossible" paddr: */
167     #define IMPOSSIBLE_PADDR 0x1212343456566767ULL
168    
169     #define DEFAULT_PCACHE_SIZE 15 /* 32 KB */
170     #define DEFAULT_PCACHE_LINESIZE 5 /* 32 bytes */
171    
172     struct r3000_cache_line {
173     uint32_t tag_paddr;
174     int tag_valid;
175     };
176     #define R3000_TAG_VALID 1
177     #define R3000_TAG_DIRTY 2
178    
179     struct r4000_cache_line {
180     char dummy;
181     };
182    
183 dpavlin 22 /********************************************************************/
184    
185     #ifdef ONEKPAGE
186     #define MIPS_IC_ENTRIES_SHIFT 8
187     #else
188     #define MIPS_IC_ENTRIES_SHIFT 10
189     #endif
190    
191     #define MIPS_N_IC_ARGS 3
192     #define MIPS_INSTR_ALIGNMENT_SHIFT 2
193     #define MIPS_IC_ENTRIES_PER_PAGE (1 << MIPS_IC_ENTRIES_SHIFT)
194     #define MIPS_PC_TO_IC_ENTRY(a) (((a)>>MIPS_INSTR_ALIGNMENT_SHIFT) \
195     & (MIPS_IC_ENTRIES_PER_PAGE-1))
196     #define MIPS_ADDR_TO_PAGENR(a) ((a) >> (MIPS_IC_ENTRIES_SHIFT \
197     + MIPS_INSTR_ALIGNMENT_SHIFT))
198    
199 dpavlin 24 #define MIPS_L2N 17
200     #define MIPS_L3N 18
201    
202     #define MIPS_MAX_VPH_TLB_ENTRIES 128
203     DYNTRANS_MISC_DECLARATIONS(mips,MIPS,uint64_t)
204     DYNTRANS_MISC64_DECLARATIONS(mips,MIPS,uint8_t)
205    
206     #if 0
207 dpavlin 22 struct mips_instr_call {
208     void (*f)(struct cpu *, struct mips_instr_call *);
209     size_t arg[MIPS_N_IC_ARGS];
210     };
211    
212     /* Translation cache struct for each physical page: */
213     struct mips_tc_physpage {
214     struct mips_instr_call ics[MIPS_IC_ENTRIES_PER_PAGE + 3];
215     uint32_t next_ofs; /* or 0 for end of chain */
216     int flags;
217     uint64_t physaddr;
218     };
219    
220     struct mips_vpg_tlb_entry {
221     uint8_t valid;
222     uint8_t writeflag;
223     unsigned char *host_page;
224     int64_t timestamp;
225     uint64_t vaddr_page;
226     uint64_t paddr_page;
227     };
228 dpavlin 24 #endif
229 dpavlin 22
230     /********************************************************************/
231    
232 dpavlin 4 struct mips_cpu {
233     struct mips_cpu_type_def cpu_type;
234    
235     struct mips_coproc *coproc[N_MIPS_COPROCS];
236    
237     int compare_register_set;
238    
239     /* Special purpose registers: */
240     uint64_t hi;
241     uint64_t lo;
242    
243 dpavlin 24 /* Dummy destination register when writing to the zero register: */
244     uint64_t scratch;
245    
246 dpavlin 4 /* General purpose registers: */
247     uint64_t gpr[N_MIPS_GPRS];
248    
249     int nullify_next; /* set to 1 if next instruction
250     is to be nullified */
251    
252     int show_trace_delay; /* 0=normal, > 0 = delay until show_trace */
253     uint64_t show_trace_addr;
254    
255     int last_was_jumptoself;
256     int jump_to_self_reg;
257    
258     int rmw; /* Read-Modify-Write */
259     int rmw_len; /* Length of rmw modification */
260     uint64_t rmw_addr; /* Address of rmw modification */
261    
262     /*
263 dpavlin 24 * NOTE: The R5900 has 128-bit registers. I'm not really sure
264 dpavlin 4 * whether they are used a lot or not, at least with code produced
265     * with gcc they are not. An important case however is lq and sq
266     * (load and store of 128-bit values). These "upper halves" of R5900
267     * quadwords can be used in those cases.
268     *
269 dpavlin 24 * hi1 and lo1 are the high 64-bit parts of the hi and lo registers.
270     * sa is a 32-bit "shift amount" register.
271     *
272 dpavlin 4 * TODO: Generalize this.
273     */
274     uint64_t gpr_quadhi[N_MIPS_GPRS];
275 dpavlin 24 uint64_t hi1;
276     uint64_t lo1;
277     uint32_t r5900_sa;
278 dpavlin 4
279    
280     /* Data and Instruction caches: */
281     unsigned char *cache[2];
282     void *cache_tags[2];
283     uint64_t cache_last_paddr[2];
284     int cache_size[2];
285     int cache_linesize[2];
286     int cache_mask[2];
287     int cache_miss_penalty[2];
288 dpavlin 10
289     /* Other stuff: */
290     uint64_t cop0_config_select1;
291 dpavlin 22
292    
293     /* NEW DYNTRANS: */
294    
295    
296     /*
297     * Instruction translation cache and Virtual->Physical->Host
298     * address translation:
299     */
300     DYNTRANS_ITC(mips)
301     VPH_TLBS(mips,MIPS)
302     VPH32(mips,MIPS,uint64_t,uint8_t)
303     VPH64(mips,MIPS,uint8_t)
304 dpavlin 4 };
305    
306    
307     /* cpu_mips.c: */
308 dpavlin 24 int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
309 dpavlin 4 void mips_cpu_tlbdump(struct machine *m, int x, int rawflag);
310     void mips_cpu_register_match(struct machine *m, char *name,
311     int writeflag, uint64_t *valuep, int *match_register);
312     void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs);
313     int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
314 dpavlin 24 int running, uint64_t addr);
315 dpavlin 4 int mips_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr);
316     int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr);
317     void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr,
318     /* uint64_t pagemask, */ int coproc_nr, uint64_t vaddr_vpn2,
319     int vaddr_asid, int x_64);
320     int mips_cpu_run(struct emul *emul, struct machine *machine);
321     void mips_cpu_dumpinfo(struct cpu *cpu);
322     void mips_cpu_list_available_types(void);
323     int mips_cpu_family_init(struct cpu_family *);
324    
325    
326     /* cpu_mips_coproc.c: */
327     struct mips_coproc *mips_coproc_new(struct cpu *cpu, int coproc_nr);
328     void mips_coproc_tlb_set_entry(struct cpu *cpu, int entrynr, int size,
329     uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,
330     int valid0, int valid1, int dirty0, int dirty1, int global, int asid,
331     int cachealgo0, int cachealgo1);
332     void coproc_register_read(struct cpu *cpu,
333 dpavlin 10 struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select);
334 dpavlin 4 void coproc_register_write(struct cpu *cpu,
335 dpavlin 10 struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int flag64,
336     int select);
337 dpavlin 4 void coproc_tlbpr(struct cpu *cpu, int readflag);
338     void coproc_tlbwri(struct cpu *cpu, int randomflag);
339     void coproc_rfe(struct cpu *cpu);
340     void coproc_eret(struct cpu *cpu);
341     void coproc_function(struct cpu *cpu, struct mips_coproc *cp, int cpnr,
342     uint32_t function, int unassemble_only, int running);
343    
344    
345     /* memory_mips.c: */
346     int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr,
347     int writeflag, size_t len, unsigned char *data);
348     int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
349     unsigned char *data, size_t len, int writeflag, int cache_flags);
350    
351 dpavlin 26 int translate_v2p_mmu3k(struct cpu *cpu, uint64_t vaddr,
352     uint64_t *return_addr, int flags);
353     int translate_v2p_mmu8k(struct cpu *cpu, uint64_t vaddr,
354     uint64_t *return_addr, int flags);
355     int translate_v2p_mmu10k(struct cpu *cpu, uint64_t vaddr,
356     uint64_t *return_addr, int flags);
357     int translate_v2p_mmu4100(struct cpu *cpu, uint64_t vaddr,
358     uint64_t *return_addr, int flags);
359     int translate_v2p_generic(struct cpu *cpu, uint64_t vaddr,
360     uint64_t *return_addr, int flags);
361 dpavlin 4
362 dpavlin 26
363 dpavlin 24 /* Dyntrans unaligned load/store: */
364     void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic,
365     int is_left, int wlen, int store);
366 dpavlin 4
367    
368 dpavlin 22 void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
369     unsigned char *host_page, int writeflag, uint64_t paddr_page);
370     void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
371     void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
372 dpavlin 24 void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
373     unsigned char *host_page, int writeflag, uint64_t paddr_page);
374     void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
375     void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
376 dpavlin 22
377    
378 dpavlin 4 #endif /* CPU_MIPS_H */

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