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#ifndef CPU_MIPS_H |
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#define CPU_MIPS_H |
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/* |
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* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_mips.h,v 1.26 2006/02/13 04:23:25 debug Exp $ |
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*/ |
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#include "misc.h" |
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/* |
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* ENABLE_MIPS16 should be defined on the cc commandline using -D, if you |
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* want it. (This is done by ./configure --mips16) |
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*/ |
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/* #define MFHILO_DELAY */ |
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struct cpu_family; |
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struct emul; |
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struct machine; |
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/* |
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* CPU type definitions: See mips_cpu_types.h. |
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*/ |
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struct mips_cpu_type_def { |
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char *name; |
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int rev; |
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int sub; |
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char flags; |
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char exc_model; /* EXC3K or EXC4K */ |
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char mmu_model; /* MMU3K or MMU4K */ |
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char isa_level; /* 1, 2, 3, 4, 5, 32, 64 */ |
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int nr_of_tlb_entries; /* 32, 48, 64, ... */ |
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char instrs_per_cycle; /* simplified, 1, 2, or 4 */ |
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int picache; |
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int pilinesize; |
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int piways; |
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int pdcache; |
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int pdlinesize; |
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int pdways; |
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int scache; |
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int slinesize; |
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int sways; |
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}; |
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#define INITIAL_PC 0xffffffffbfc00000ULL |
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#define INITIAL_STACK_POINTER (0xffffffffa0008000ULL - 256) |
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/* |
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* Coproc 0: |
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*/ |
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#define N_MIPS_COPROC_REGS 32 |
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struct mips_tlb { |
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uint64_t hi; |
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uint64_t lo0; |
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uint64_t lo1; |
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uint64_t mask; |
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}; |
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/* |
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* Coproc 1: |
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*/ |
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#define N_MIPS_FCRS 32 |
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struct mips_coproc { |
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int coproc_nr; |
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uint64_t reg[N_MIPS_COPROC_REGS]; |
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/* Only for COP0: */ |
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struct mips_tlb *tlbs; |
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int nr_of_tlbs; |
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/* Only for COP1: floating point control registers */ |
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/* (Maybe also for COP0?) */ |
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uint64_t fcr[N_MIPS_FCRS]; |
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}; |
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#define N_MIPS_COPROCS 4 |
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#define N_MIPS_GPRS 32 /* General purpose registers */ |
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#define N_MIPS_FPRS 32 /* Floating point registers */ |
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/* |
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* These should all be 2 characters wide: |
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* |
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* NOTE: These are for 32-bit ABIs. For the 64-bit ABI, registers 8..11 |
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* are used to pass arguments and are then called "a4".."a7". |
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* |
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* TODO: Should there be two different variants of this? It's not really |
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* possible to figure out in some easy way if the code running was |
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* written for a 32-bit or 64-bit ABI. |
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*/ |
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#define MIPS_REGISTER_NAMES { \ |
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"zr", "at", "v0", "v1", "a0", "a1", "a2", "a3", \ |
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"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \ |
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"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \ |
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"t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra" } |
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#define MIPS_GPR_ZERO 0 /* zero */ |
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#define MIPS_GPR_AT 1 /* at */ |
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#define MIPS_GPR_V0 2 /* v0 */ |
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#define MIPS_GPR_V1 3 /* v1 */ |
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#define MIPS_GPR_A0 4 /* a0 */ |
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#define MIPS_GPR_A1 5 /* a1 */ |
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#define MIPS_GPR_A2 6 /* a2 */ |
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#define MIPS_GPR_A3 7 /* a3 */ |
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#define MIPS_GPR_T0 8 /* t0 */ |
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#define MIPS_GPR_T1 9 /* t1 */ |
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#define MIPS_GPR_T2 10 /* t2 */ |
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#define MIPS_GPR_T3 11 /* t3 */ |
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#define MIPS_GPR_T4 12 /* t4 */ |
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#define MIPS_GPR_T5 13 /* t5 */ |
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#define MIPS_GPR_T6 14 /* t6 */ |
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#define MIPS_GPR_T7 15 /* t7 */ |
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#define MIPS_GPR_S0 16 /* s0 */ |
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#define MIPS_GPR_S1 17 /* s1 */ |
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#define MIPS_GPR_S2 18 /* s2 */ |
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#define MIPS_GPR_S3 19 /* s3 */ |
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#define MIPS_GPR_S4 20 /* s4 */ |
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#define MIPS_GPR_S5 21 /* s5 */ |
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#define MIPS_GPR_S6 22 /* s6 */ |
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#define MIPS_GPR_S7 23 /* s7 */ |
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#define MIPS_GPR_T8 24 /* t8 */ |
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#define MIPS_GPR_T9 25 /* t9 */ |
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#define MIPS_GPR_K0 26 /* k0 */ |
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#define MIPS_GPR_K1 27 /* k1 */ |
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#define MIPS_GPR_GP 28 /* gp */ |
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#define MIPS_GPR_SP 29 /* sp */ |
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#define MIPS_GPR_FP 30 /* fp */ |
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#define MIPS_GPR_RA 31 /* ra */ |
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/* Meaning of delay_slot: */ |
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#define NOT_DELAYED 0 |
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#define DELAYED 1 |
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#define TO_BE_DELAYED 2 |
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#define EXCEPTION_IN_DELAY_SLOT 0x100 |
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#define N_HI6 64 |
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#define N_SPECIAL 64 |
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#define N_REGIMM 32 |
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/******************************* OLD: *****************************/ |
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/* Number of "tiny" translation cache entries: */ |
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#define N_TRANSLATION_CACHE_INSTR 5 |
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#define N_TRANSLATION_CACHE_DATA 5 |
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struct translation_cache_entry { |
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int wf; |
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uint64_t vaddr_pfn; |
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uint64_t paddr; |
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}; |
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/* This should be a value which the program counter |
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can "never" have: */ |
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#define PC_LAST_PAGE_IMPOSSIBLE_VALUE 3 |
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/* An "impossible" paddr: */ |
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#define IMPOSSIBLE_PADDR 0x1212343456566767ULL |
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#define DEFAULT_PCACHE_SIZE 15 /* 32 KB */ |
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#define DEFAULT_PCACHE_LINESIZE 5 /* 32 bytes */ |
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struct r3000_cache_line { |
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uint32_t tag_paddr; |
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int tag_valid; |
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}; |
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#define R3000_TAG_VALID 1 |
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#define R3000_TAG_DIRTY 2 |
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struct r4000_cache_line { |
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char dummy; |
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}; |
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/********************************************************************/ |
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#ifdef ONEKPAGE |
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#define MIPS_IC_ENTRIES_SHIFT 8 |
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#else |
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#define MIPS_IC_ENTRIES_SHIFT 10 |
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#endif |
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#define MIPS_N_IC_ARGS 3 |
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#define MIPS_INSTR_ALIGNMENT_SHIFT 2 |
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#define MIPS_IC_ENTRIES_PER_PAGE (1 << MIPS_IC_ENTRIES_SHIFT) |
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#define MIPS_PC_TO_IC_ENTRY(a) (((a)>>MIPS_INSTR_ALIGNMENT_SHIFT) \ |
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& (MIPS_IC_ENTRIES_PER_PAGE-1)) |
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#define MIPS_ADDR_TO_PAGENR(a) ((a) >> (MIPS_IC_ENTRIES_SHIFT \ |
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+ MIPS_INSTR_ALIGNMENT_SHIFT)) |
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struct mips_instr_call { |
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void (*f)(struct cpu *, struct mips_instr_call *); |
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size_t arg[MIPS_N_IC_ARGS]; |
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}; |
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/* Translation cache struct for each physical page: */ |
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struct mips_tc_physpage { |
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struct mips_instr_call ics[MIPS_IC_ENTRIES_PER_PAGE + 3]; |
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uint32_t next_ofs; /* or 0 for end of chain */ |
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int flags; |
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uint64_t physaddr; |
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}; |
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#define MIPS_MAX_VPH_TLB_ENTRIES 128 |
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struct mips_vpg_tlb_entry { |
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uint8_t valid; |
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uint8_t writeflag; |
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unsigned char *host_page; |
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int64_t timestamp; |
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uint64_t vaddr_page; |
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uint64_t paddr_page; |
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}; |
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/******************************* OLD: *****************************/ |
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#define BINTRANS_DONT_RUN_NEXT 0x1000000 |
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#define BINTRANS_N_MASK 0x0ffffff |
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#define N_SAFE_BINTRANS_LIMIT_SHIFT 14 |
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#define N_SAFE_BINTRANS_LIMIT ((1 << (N_SAFE_BINTRANS_LIMIT_SHIFT - 1)) - 1) |
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#define N_BINTRANS_VADDR_TO_HOST 20 |
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/* Virtual to host address translation tables: */ |
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struct vth32_table { |
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void *haddr_entry[1024 * 2]; |
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uint32_t paddr_entry[1024]; |
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uint32_t *bintrans_chunks[1024]; |
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struct vth32_table *next_free; |
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int refcount; |
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}; |
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/********************************************************************/ |
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struct mips_cpu { |
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struct mips_cpu_type_def cpu_type; |
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struct mips_coproc *coproc[N_MIPS_COPROCS]; |
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int compare_register_set; |
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/* Special purpose registers: */ |
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uint64_t pc_last; /* PC of last instruction */ |
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uint64_t hi; |
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uint64_t lo; |
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/* General purpose registers: */ |
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uint64_t gpr[N_MIPS_GPRS]; |
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/* |
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* The translation_cached stuff is used to speed up the |
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* most recent lookups into the TLB. Whenever the TLB is |
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* written to, translation_cached[] must be filled with zeros. |
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*/ |
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#ifdef USE_TINY_CACHE |
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struct translation_cache_entry |
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translation_cache_instr[N_TRANSLATION_CACHE_INSTR]; |
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struct translation_cache_entry |
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translation_cache_data[N_TRANSLATION_CACHE_DATA]; |
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#endif |
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/* |
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* For faster memory lookup when running instructions: |
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* |
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* Reading memory to load instructions is a very common thing in the |
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* emulator, and an instruction is very often read from the address |
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* following the previously executed instruction. That means that we |
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* don't have to go through the TLB each time. |
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* |
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* We then get the vaddr -> paddr translation for free. There is an |
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* even better case when the paddr is a RAM address (as opposed to an |
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* address in a memory mapped device). Then we can figure out the |
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* address in the host's memory directly, and skip the paddr -> host |
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* address calculation as well. |
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* |
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* A modification to the TLB should set the virtual_page variable to |
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* an "impossible" value, so that there won't be a hit on the next |
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* instruction. |
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*/ |
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uint64_t pc_last_virtual_page; |
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uint64_t pc_last_physical_page; |
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unsigned char *pc_last_host_4k_page; |
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/* MIPS Bintrans: */ |
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int dont_run_next_bintrans; |
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int bintrans_instructions_executed; /* set to the |
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number of bintranslated instructions executed |
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when running a bintrans codechunk */ |
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int pc_bintrans_paddr_valid; |
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uint64_t pc_bintrans_paddr; |
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unsigned char *pc_bintrans_host_4kpage; |
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/* Chunk base address: */ |
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unsigned char *chunk_base_address; |
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/* This should work for 32-bit MIPS emulation: */ |
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struct vth32_table *vaddr_to_hostaddr_nulltable; |
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struct vth32_table *vaddr_to_hostaddr_r2k3k_icachetable; |
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struct vth32_table *vaddr_to_hostaddr_r2k3k_dcachetable; |
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struct vth32_table **vaddr_to_hostaddr_table0_kernel; |
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struct vth32_table **vaddr_to_hostaddr_table0_cacheisol_i; |
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struct vth32_table **vaddr_to_hostaddr_table0_cacheisol_d; |
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struct vth32_table **vaddr_to_hostaddr_table0_user; |
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struct vth32_table **vaddr_to_hostaddr_table0; /* should point to kernel or user */ |
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struct vth32_table *next_free_vth_table; |
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/* Testing... */ |
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unsigned char **host_OLD_load; |
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unsigned char **host_OLD_store; |
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unsigned char **host_load_orig; |
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unsigned char **host_store_orig; |
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unsigned char **huge_r2k3k_cache_table; |
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/* For 64-bit (generic) emulation: */ |
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unsigned char *(*fast_vaddr_to_hostaddr)(struct cpu *cpu, |
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uint64_t vaddr, int writeflag); |
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int bintrans_next_index; |
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int bintrans_data_writable[N_BINTRANS_VADDR_TO_HOST]; |
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uint64_t bintrans_data_vaddr[N_BINTRANS_VADDR_TO_HOST]; |
| 348 |
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unsigned char *bintrans_data_hostpage[N_BINTRANS_VADDR_TO_HOST]; |
| 349 |
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| 350 |
dpavlin |
10 |
void (*bintrans_load_32bit)(struct cpu *); /* Note: incorrect args */ |
| 351 |
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void (*bintrans_store_32bit)(struct cpu *); /* Note: incorrect args */ |
| 352 |
dpavlin |
4 |
void (*bintrans_jump_to_32bit_pc)(struct cpu *); |
| 353 |
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void (*bintrans_simple_exception)(struct cpu *, int); |
| 354 |
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void (*bintrans_fast_rfe)(struct cpu *); |
| 355 |
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void (*bintrans_fast_eret)(struct cpu *); |
| 356 |
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void (*bintrans_fast_tlbwri)(struct cpu *, int); |
| 357 |
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void (*bintrans_fast_tlbpr)(struct cpu *, int); |
| 358 |
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| 359 |
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#ifdef ENABLE_MIPS16 |
| 360 |
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int mips16; /* non-zero if MIPS16 code is allowed */ |
| 361 |
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uint16_t mips16_extend; /* set on 'extend' instructions to the entire 16-bit extend instruction */ |
| 362 |
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#endif |
| 363 |
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| 364 |
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#ifdef ENABLE_INSTRUCTION_DELAYS |
| 365 |
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int instruction_delay; |
| 366 |
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#endif |
| 367 |
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| 368 |
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uint64_t delay_jmpaddr; /* only used if delay_slot > 0 */ |
| 369 |
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int delay_slot; |
| 370 |
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int nullify_next; /* set to 1 if next instruction |
| 371 |
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is to be nullified */ |
| 372 |
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| 373 |
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/* This is set to non-zero, if it is possible at all that an |
| 374 |
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interrupt will occur. */ |
| 375 |
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int cached_interrupt_is_possible; |
| 376 |
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| 377 |
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int show_trace_delay; /* 0=normal, > 0 = delay until show_trace */ |
| 378 |
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uint64_t show_trace_addr; |
| 379 |
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| 380 |
|
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int last_was_jumptoself; |
| 381 |
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int jump_to_self_reg; |
| 382 |
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| 383 |
|
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#ifdef MFHILO_DELAY |
| 384 |
|
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int mfhi_delay; /* instructions since last mfhi */ |
| 385 |
|
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int mflo_delay; /* instructions since last mflo */ |
| 386 |
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#endif |
| 387 |
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| 388 |
|
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int rmw; /* Read-Modify-Write */ |
| 389 |
|
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int rmw_len; /* Length of rmw modification */ |
| 390 |
|
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uint64_t rmw_addr; /* Address of rmw modification */ |
| 391 |
|
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|
| 392 |
|
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/* |
| 393 |
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* TODO: The R5900 has 128-bit registers. I'm not really sure |
| 394 |
|
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* whether they are used a lot or not, at least with code produced |
| 395 |
|
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* with gcc they are not. An important case however is lq and sq |
| 396 |
|
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* (load and store of 128-bit values). These "upper halves" of R5900 |
| 397 |
|
|
* quadwords can be used in those cases. |
| 398 |
|
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* |
| 399 |
|
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* TODO: Generalize this. |
| 400 |
|
|
*/ |
| 401 |
|
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uint64_t gpr_quadhi[N_MIPS_GPRS]; |
| 402 |
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|
| 403 |
|
|
|
| 404 |
|
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/* |
| 405 |
|
|
* Statistics: |
| 406 |
|
|
*/ |
| 407 |
|
|
long stats_opcode[N_HI6]; |
| 408 |
|
|
long stats__special[N_SPECIAL]; |
| 409 |
|
|
long stats__regimm[N_REGIMM]; |
| 410 |
|
|
long stats__special2[N_SPECIAL]; |
| 411 |
|
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|
| 412 |
|
|
/* Data and Instruction caches: */ |
| 413 |
|
|
unsigned char *cache[2]; |
| 414 |
|
|
void *cache_tags[2]; |
| 415 |
|
|
uint64_t cache_last_paddr[2]; |
| 416 |
|
|
int cache_size[2]; |
| 417 |
|
|
int cache_linesize[2]; |
| 418 |
|
|
int cache_mask[2]; |
| 419 |
|
|
int cache_miss_penalty[2]; |
| 420 |
dpavlin |
10 |
|
| 421 |
|
|
/* Other stuff: */ |
| 422 |
|
|
uint64_t cop0_config_select1; |
| 423 |
dpavlin |
22 |
|
| 424 |
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|
|
| 425 |
|
|
/* NEW DYNTRANS: */ |
| 426 |
|
|
|
| 427 |
|
|
|
| 428 |
|
|
/* |
| 429 |
|
|
* Instruction translation cache and Virtual->Physical->Host |
| 430 |
|
|
* address translation: |
| 431 |
|
|
*/ |
| 432 |
|
|
DYNTRANS_ITC(mips) |
| 433 |
|
|
VPH_TLBS(mips,MIPS) |
| 434 |
|
|
VPH32(mips,MIPS,uint64_t,uint8_t) |
| 435 |
|
|
VPH64(mips,MIPS,uint8_t) |
| 436 |
dpavlin |
4 |
}; |
| 437 |
|
|
|
| 438 |
|
|
|
| 439 |
|
|
/* cpu_mips.c: */ |
| 440 |
|
|
void mips_cpu_show_full_statistics(struct machine *m); |
| 441 |
|
|
void mips_cpu_tlbdump(struct machine *m, int x, int rawflag); |
| 442 |
|
|
void mips_cpu_register_match(struct machine *m, char *name, |
| 443 |
|
|
int writeflag, uint64_t *valuep, int *match_register); |
| 444 |
|
|
void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs); |
| 445 |
|
|
int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
| 446 |
|
|
int running, uint64_t addr, int bintrans); |
| 447 |
|
|
int mips_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr); |
| 448 |
|
|
int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr); |
| 449 |
|
|
void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr, |
| 450 |
|
|
/* uint64_t pagemask, */ int coproc_nr, uint64_t vaddr_vpn2, |
| 451 |
|
|
int vaddr_asid, int x_64); |
| 452 |
|
|
void mips_cpu_cause_simple_exception(struct cpu *cpu, int exc_code); |
| 453 |
|
|
int mips_cpu_run(struct emul *emul, struct machine *machine); |
| 454 |
|
|
void mips_cpu_dumpinfo(struct cpu *cpu); |
| 455 |
|
|
void mips_cpu_list_available_types(void); |
| 456 |
|
|
int mips_cpu_family_init(struct cpu_family *); |
| 457 |
|
|
|
| 458 |
|
|
|
| 459 |
|
|
/* cpu_mips_coproc.c: */ |
| 460 |
|
|
struct mips_coproc *mips_coproc_new(struct cpu *cpu, int coproc_nr); |
| 461 |
|
|
void mips_coproc_tlb_set_entry(struct cpu *cpu, int entrynr, int size, |
| 462 |
|
|
uint64_t vaddr, uint64_t paddr0, uint64_t paddr1, |
| 463 |
|
|
int valid0, int valid1, int dirty0, int dirty1, int global, int asid, |
| 464 |
|
|
int cachealgo0, int cachealgo1); |
| 465 |
dpavlin |
22 |
void mips_OLD_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
| 466 |
dpavlin |
4 |
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
| 467 |
|
|
void clear_all_chunks_from_all_tables(struct cpu *cpu); |
| 468 |
dpavlin |
14 |
void mips_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int); |
| 469 |
dpavlin |
4 |
void coproc_register_read(struct cpu *cpu, |
| 470 |
dpavlin |
10 |
struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select); |
| 471 |
dpavlin |
4 |
void coproc_register_write(struct cpu *cpu, |
| 472 |
dpavlin |
10 |
struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int flag64, |
| 473 |
|
|
int select); |
| 474 |
dpavlin |
4 |
void coproc_tlbpr(struct cpu *cpu, int readflag); |
| 475 |
|
|
void coproc_tlbwri(struct cpu *cpu, int randomflag); |
| 476 |
|
|
void coproc_rfe(struct cpu *cpu); |
| 477 |
|
|
void coproc_eret(struct cpu *cpu); |
| 478 |
|
|
void coproc_function(struct cpu *cpu, struct mips_coproc *cp, int cpnr, |
| 479 |
|
|
uint32_t function, int unassemble_only, int running); |
| 480 |
|
|
|
| 481 |
|
|
|
| 482 |
|
|
/* memory_mips.c: */ |
| 483 |
|
|
int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr, |
| 484 |
|
|
int writeflag, size_t len, unsigned char *data); |
| 485 |
|
|
int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
| 486 |
|
|
unsigned char *data, size_t len, int writeflag, int cache_flags); |
| 487 |
|
|
|
| 488 |
|
|
|
| 489 |
|
|
/* mips16.c: */ |
| 490 |
|
|
int mips16_to_32(struct cpu *cpu, unsigned char *instr16, unsigned char *instr); |
| 491 |
|
|
|
| 492 |
|
|
|
| 493 |
dpavlin |
22 |
/* NEW DYNTRANS: */ |
| 494 |
|
|
void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
| 495 |
|
|
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
| 496 |
|
|
void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
| 497 |
|
|
void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
| 498 |
|
|
|
| 499 |
|
|
|
| 500 |
dpavlin |
4 |
#endif /* CPU_MIPS_H */ |
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