/[gxemul]/trunk/src/include/cpu_m88k.h
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Contents of /trunk/src/include/cpu_m88k.h

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Revision 44 - (show annotations)
Mon Oct 8 16:22:56 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 9574 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1632 2007/09/11 21:46:35 debug Exp $
20070616	Implementing the MIPS32/64 revision 2 "ror" instruction.
20070617	Adding a struct for each physpage which keeps track of which
		ranges within that page (base offset, length) that are
		continuously translatable. When running with native code
		generation enabled (-b), a range is added after each read-
		ahead loop.
		Experimenting with using the physical program counter sample
		data (implemented 20070608) together with the "translatable
		range" information, to figure out which physical address ranges
		would be worth translating to native code (if the number of
		samples falling within a range is above a certain threshold).
20070618	Adding automagic building of .index comment files for
		src/file/, src/promemul/, src src/useremul/ as well.
		Adding a "has been translated" bit to the ranges, so that only
		not-yet-translated ranges will be sampled.
20070619	Moving src/cpu.c and src/memory_rw.c into src/cpus/,
		src/device.c into src/devices/, and src/machine.c into
		src/machines/.
		Creating a skeleton cc/ld native backend module; beginning on
		the function which will detect cc command line, etc.
20070620	Continuing on the native code generation infrastructure.
20070621	Moving src/x11.c and src/console.c into a new src/console/
		subdir (for everything that is console or framebuffer related).
		Moving src/symbol*.c into a new src/symbol/, which should
		contain anything that is symbol handling related.
20070624	Making the program counter sampling threshold a "settings
		variable" (sampling_threshold), i.e. it can now be changed
		during runtime.
		Switching the RELEASE notes format from plain text to HTML.
		If the TMPDIR environment variable is set, it is used instead
		of "/tmp" for temporary files.
		Continuing on the cc/ld backend: simple .c code is generated,
		the compiler and linker are called, etc.
		Adding detection of host architecture to the configure script
		(again), and adding icache invalidation support (only
		implemented for Alpha hosts so far).
20070625	Simplifying the program counter sampling mechanism.
20070626	Removing the cc/ld native code generation stuff, program
		counter sampling, etc; it would not have worked well in the
		general case.
20070627	Removing everything related to native code generation.
20070629	Removing the (practically unusable) support for multiple
		emulations. (The single emulation allowed now still supports
		multiple simultaneous machines, as before.)
		Beginning on PCCTWO and M88K interrupts.
20070723	Adding a dummy skeleton for emulation of M32R processors.
20070901	Fixing a warning found by "gcc version 4.3.0 20070817
		(experimental)" on amd64.
20070905	Removing some more traces of the old "multiple emulations"
		code.
		Also looking in /usr/local/include and /usr/local/lib for
		X11 libs, when running configure.
20070909	Minor updates to the guest OS install instructions, in
		preparation for the NetBSD 4.0 release.
20070918	More testing of NetBSD 4.0 RC1.

1 #ifndef CPU_M88K_H
2 #define CPU_M88K_H
3
4 /*
5 * Copyright (C) 2007 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cpu_m88k.h,v 1.22 2007/07/20 09:03:33 debug Exp $
32 */
33
34 #include "misc.h"
35 #include "interrupt.h"
36
37 #include "m88k_psl.h"
38
39 struct cpu_family;
40
41 /* M88K CPU types: */
42 struct m88k_cpu_type_def {
43 char *name;
44 int type;
45 uint32_t pid;
46 };
47
48 #define M88K_PID(arn,vn) ((arn << M88K_ARN_SHIFT) | (vn << M88K_VN_SHIFT))
49
50 #define M88K_CPU_TYPE_DEFS { \
51 { "88100", 88100, M88K_PID(M88K_ARN_88100,3) }, \
52 { "88110", 88110, M88K_PID(M88K_ARN_88110,0) }, \
53 { NULL, 0, 0 } \
54 }
55
56 /* Control register names: */
57 #define N_M88K_CONTROL_REGS 64
58 #define M88K_CR_NAMES { \
59 "PID", "PSR", "EPSR", "SSBR", /* 0 .. 3 */ \
60 "SXIP", "SNIP", "SFIP", "VBR", /* 4 .. 7 */ \
61 "DMT0", "DMD0", "DMA0", "DMT1", /* 8 .. 11 */ \
62 "DMD1", "DMA1", "DMT2", "DMD2", /* 12 .. 15 */ \
63 "DMA2", "SR0", "SR1", "SR2", /* 16 .. 19 */ \
64 "SR3", "CR21", "CR22", "CR23", /* 20 .. 23 */ \
65 "CR24", "CR25", "CR26", "CR27", /* 24 .. 27 */ \
66 "CR28", "CR29", "CR30", "CR31", /* 28 .. 31 */ \
67 "CR32", "CR33", "CR34", "CR35", /* 32 .. 35 */ \
68 "CR36", "CR37", "CR38", "CR39", /* 36 .. 39 */ \
69 "CR40", "CR41", "CR42", "CR43", /* 40 .. 43 */ \
70 "CR44", "CR45", "CR46", "CR47", /* 44 .. 47 */ \
71 "CR48", "CR49", "CR50", "CR51", /* 48 .. 51 */ \
72 "CR52", "CR53", "CR54", "CR55", /* 52 .. 55 */ \
73 "CR56", "CR57", "CR58", "CR59", /* 56 .. 59 */ \
74 "CR60", "CR61", "CR62", "CR63" /* 60 .. 63 */ }
75
76 #define M88K_CR_PID 0
77 #define M88K_CR_PSR 1
78 #define M88K_CR_EPSR 2
79 #define M88K_CR_SSBR 3
80 #define M88K_CR_SXIP 4
81 #define M88K_CR_SNIP 5
82 #define M88K_CR_SFIP 6
83 #define M88K_CR_VBR 7
84 #define M88K_CR_DMT0 8
85 #define M88K_CR_DMD0 9
86 #define M88K_CR_DMA0 10
87 #define M88K_CR_DMT1 11
88 #define M88K_CR_DMD1 12
89 #define M88K_CR_DMA1 13
90 #define M88K_CR_DMT2 14
91 #define M88K_CR_DMD2 15
92 #define M88K_CR_DMA2 16
93 #define M88K_CR_SR0 17
94 #define M88K_CR_SR1 18
95 #define M88K_CR_SR2 19
96 #define M88K_CR_SR3 20
97
98 /* MVME197 extended control registers: */
99 #define M88K_CR_NAMES_197 { \
100 "PID", "PSR", "EPSR", "SSBR", /* 0 .. 3 */ \
101 "EXIP", "ENIP", "SFIP", "VBR", /* 4 .. 7 */ \
102 "DMT0", "DMD0", "DMA0", "DMT1", /* 8 .. 11 */ \
103 "DMD1", "DMA1", "DMT2", "DMD2", /* 12 .. 15 */ \
104 "SRX", "SR0", "SR1", "SR2", /* 16 .. 19 */ \
105 "SR3", "CR21", "CR22", "CR23", /* 20 .. 23 */ \
106 "CR24", "ICMD", "ICTL", "ISAR", /* 24 .. 27 */ \
107 "ISAP", "IUAP", "IIR", "IBP", /* 28 .. 31 */ \
108 "IPPU", "IPPL", "ISR", "ILAR", /* 32 .. 35 */ \
109 "IPAR", "CR37", "CR38", "CR39", /* 36 .. 39 */ \
110 "DCMD", "DCTL", "DSAR", "DSAP", /* 40 .. 43 */ \
111 "DUAP", "DIR", "DBP", "DPPU", /* 44 .. 47 */ \
112 "DPPL", "DSR", "DLAR", "DPAR", /* 48 .. 51 */ \
113 "CR52", "CR53", "CR54", "CR55", /* 52 .. 55 */ \
114 "CR56", "CR57", "CR58", "CR59", /* 56 .. 59 */ \
115 "CR60", "CR61", "CR62", "CR63" /* 60 .. 63 */ }
116
117 #define M88K_CR_EXIP 4
118 #define M88K_CR_ENIP 5
119 #define M88K_CR_SRX 16
120 #define M88K_CR_ICMD 25
121 #define M88K_CR_ICTL 26
122 #define M88K_CR_ISAR 27
123 #define M88K_CR_ISAP 28
124 #define M88K_CR_IUAP 29
125 #define M88K_CR_IIR 30
126 #define M88K_CR_IBP 31
127 #define M88K_CR_IPPU 32
128 #define M88K_CR_IPPL 33
129 #define M88K_CR_ISR 34
130 #define M88K_CR_ILAR 35
131 #define M88K_CR_IPAR 36
132 #define M88K_CR_DCMD 40
133 #define M88K_CR_DCTL 41
134 #define M88K_CR_DSAR 42
135 #define M88K_CR_DSAP 43
136 #define M88K_CR_DUAP 44
137 #define M88K_CR_DIR 45
138 #define M88K_CR_DBP 46
139 #define M88K_CR_DPPU 47
140 #define M88K_CR_DPPL 48
141 #define M88K_CR_DSR 49
142 #define M88K_CR_DLAR 50
143 #define M88K_CR_DPAR 51
144
145 #define N_M88K_FPU_CONTROL_REGS 64
146
147
148 #define M88K_N_IC_ARGS 3
149 #define M88K_INSTR_ALIGNMENT_SHIFT 2
150 #define M88K_IC_ENTRIES_SHIFT 10
151 #define M88K_IC_ENTRIES_PER_PAGE (1 << M88K_IC_ENTRIES_SHIFT)
152 #define M88K_PC_TO_IC_ENTRY(a) (((a)>>M88K_INSTR_ALIGNMENT_SHIFT) \
153 & (M88K_IC_ENTRIES_PER_PAGE-1))
154 #define M88K_ADDR_TO_PAGENR(a) ((a) >> (M88K_IC_ENTRIES_SHIFT \
155 + M88K_INSTR_ALIGNMENT_SHIFT))
156
157 DYNTRANS_MISC_DECLARATIONS(m88k,M88K,uint32_t)
158
159 #define M88K_MAX_VPH_TLB_ENTRIES 128
160
161
162 #define N_M88K_REGS 32
163
164 /* Register r0 is always zero, r1 is the return address on function calls. */
165 #define M88K_ZERO_REG 0
166 #define M88K_RETURN_REG 1
167
168 #define M88K_CMP_HS 0x00000800
169 #define M88K_CMP_LO 0x00000400
170 #define M88K_CMP_LS 0x00000200
171 #define M88K_CMP_HI 0x00000100
172 #define M88K_CMP_GE 0x00000080
173 #define M88K_CMP_LT 0x00000040
174 #define M88K_CMP_LE 0x00000020
175 #define M88K_CMP_GT 0x00000010
176 #define M88K_CMP_NE 0x00000008
177 #define M88K_CMP_EQ 0x00000004
178
179 /* Exception numbers: */
180 #define M88K_EXCEPTION_RESET 0
181 #define M88K_EXCEPTION_INTERRUPT 1
182 #define M88K_EXCEPTION_INSTRUCTION_ACCESS 2
183 #define M88K_EXCEPTION_DATA_ACCESS 3
184 #define M88K_EXCEPTION_MISALIGNED_ACCESS 4
185 #define M88K_EXCEPTION_UNIMPLEMENTED_OPCODE 5
186 #define M88K_EXCEPTION_PRIVILEGE_VIOLATION 6
187 #define M88K_EXCEPTION_BOUNDS_CHECK_VIOLATION 7
188 #define M88K_EXCEPTION_ILLEGAL_INTEGER_DIVIDE 8
189 #define M88K_EXCEPTION_INTEGER_OVERFLOW 9
190 #define M88K_EXCEPTION_ERROR 10
191 #define M88K_EXCEPTION_SFU1_PRECISE 114
192 #define M88K_EXCEPTION_SFU1_IMPRECISE 115
193 #define M88K_EXCEPTION_USER_TRAPS_START 128
194
195 /* A reserved/unimplemented instruction, used for PROM calls: */
196 #define M88K_PROM_INSTR 0xf400fc92
197
198
199 /*
200 * M88200/88204 CMMU:
201 */
202
203 #define MAX_M8820X_CMMUS 8
204 #define M8820X_LENGTH 0x1000
205 #define N_M88200_BATC_REGS 10
206 #define N_M88200_PATC_ENTRIES 56
207 #define M8820X_PATC_SUPERVISOR_BIT 0x00000001
208
209 struct m8820x_cmmu {
210 uint32_t reg[M8820X_LENGTH / sizeof(uint32_t)];
211 uint32_t batc[N_M88200_BATC_REGS];
212 uint32_t patc_v_and_control[N_M88200_PATC_ENTRIES];
213 uint32_t patc_p_and_supervisorbit[N_M88200_PATC_ENTRIES];
214 int patc_update_index;
215 };
216
217
218 struct m88k_cpu {
219 struct m88k_cpu_type_def cpu_type;
220
221 /*
222 * General-Purpose Registers:
223 *
224 * 32 (N_M88K_REGS) registers, plus one which is always zero. (This
225 * is to support st.d with d = r31. ld.d with d=r31 is converted to
226 * just ld. TODO)
227 */
228 uint32_t r[N_M88K_REGS+1];
229
230 /* Destination scratch register for non-nop instructions with d=r0: */
231 uint32_t zero_scratch;
232
233 /* Control Registers: */
234 uint32_t cr[N_M88K_CONTROL_REGS];
235
236 /* Floating Point registers: */
237 uint32_t fcr[N_M88K_FPU_CONTROL_REGS];
238
239 /* Current interrupt assertion: */
240 int irq_asserted;
241
242 /* CMMUs (Cache/Memory Management Units): */
243 struct m8820x_cmmu *cmmu[MAX_M8820X_CMMUS];
244
245 /* Current memory transaction fault registers: */
246 uint32_t dmt[2];
247 uint32_t dmd[2];
248 uint32_t dma[2];
249
250 /* Delayed-branch target (for exception handling): */
251 uint32_t delay_target;
252
253
254 /*
255 * Instruction translation cache, internal TLB structure, and 32-bit
256 * virtual -> physical -> host address translation arrays for both
257 * normal access and for the special .usr access mode (available in
258 * supervisor mode).
259 */
260 DYNTRANS_ITC(m88k)
261 VPH_TLBS(m88k,M88K)
262 VPH32(m88k,M88K)
263 VPH32EXTENDED(m88k,M88K,usr)
264 };
265
266
267 /* cpu_m88k.c: */
268 int m88k_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
269 int m88k_run_instr(struct cpu *cpu);
270 void m88k_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
271 unsigned char *host_page, int writeflag, uint64_t paddr_page);
272 void m88k_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
273 void m88k_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
274 int m88k_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
275 unsigned char *data, size_t len, int writeflag, int cache_flags);
276 int m88k_cpu_family_init(struct cpu_family *);
277 void m88k_ldcr(struct cpu *cpu, uint32_t *r32ptr, int cr);
278 void m88k_stcr(struct cpu *cpu, uint32_t value, int cr, int rte);
279 void m88k_fstcr(struct cpu *cpu, uint32_t value, int fcr);
280 void m88k_exception(struct cpu *cpu, int vector, int is_trap);
281
282 /* memory_m88k.c: */
283 int m88k_translate_v2p(struct cpu *cpu, uint64_t vaddr,
284 uint64_t *return_addr, int flags);
285
286
287 #endif /* CPU_M88K_H */

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