/[gxemul]/trunk/src/include/cpu_m88k.h
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Contents of /trunk/src/include/cpu_m88k.h

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Revision 42 - (show annotations)
Mon Oct 8 16:22:32 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 9641 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501	Continuing a little on m88k disassembly (control registers,
		more instructions).
		Adding a dummy mvme88k machine mode.
20070502	Re-adding MIPS load/store alignment exceptions.
20070503	Implementing more of the M88K disassembly code.
20070504	Adding disassembly of some more M88K load/store instructions.
		Implementing some relatively simple M88K instructions (br.n,
		xor[.u] imm, and[.u] imm).
20070505	Implementing M88K three-register and, or, xor, and jmp[.n],
		bsr[.n] including function call trace stuff.
		Applying a patch from Bruce M. Simpson which implements the
		SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
		the yamon PROM emulation.
20070506	Implementing M88K bb0[.n] and bb1[.n], and skeletons for
		ldcr and stcr (although no control regs are implemented yet).
20070509	Found and fixed the bug which caused Linux for QEMU_MIPS to
		stop working in 0.4.5.1: It was a faulty change to the MIPS
		'sc' and 'scd' instructions I made while going through gcc -W
		warnings on 20070428.
20070510	Updating the Linux/QEMU_MIPS section in guestoses.html to
		use mips-test-0.2.tar.gz instead of 0.1.
		A big thank you to Miod Vallat for sending me M88K manuals.
		Implementing more M88K instructions (addu, subu, div[u], mulu,
		ext[u], clr, set, cmp).
20070511	Fixing bugs in the M88K "and" and "and.u" instructions (found
		by comparing against the manual).
		Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
		generated)) and some more control register details.
		Cleanup: Removing the experimental AVR emulation mode and
		corresponding devices; AVR emulation wasn't really meaningful.
		Implementing autogeneration of most M88K loads/stores. The
		rectangle drawing demo (with -O0) for M88K runs :-)
		Beginning on M88K exception handling.
		More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
		Adding some skeleton MVME PROM ("BUG") emulation.
20070512	Fixing a bug in the M88K cmp instruction.
		Adding the M88K lda (scaled register) instruction.
		Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
		Removing the unused tick_hz stuff from the machine struct.
		Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
		far enough to display the Copyright banner :-)
		Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
		Adding a dev_mvme187, for MVME187-specific devices/registers.
		OpenBSD/mvme88k prints more boot messages. :)
20070515	Continuing on MVME187 emulation (adding more devices, beginning
		on the CMMUs, etc).
		Adding the M88K and.c, xor.c, and or.c instructions, and making
		sure that mul, div, etc cause exceptions if executed when SFD1
		is disabled.
20070517	Continuing on M88K and MVME187 emulation in general; moving
		the CMMU registers to the CPU struct, separating dev_pcc2 from
		dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
		Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
		Implementing the clock part of dev_mk48txx.
		Implementing the M88K fstcr and xcr instructions.
		Implementing m88k_cpu_tlbdump().
		Beginning on the implementation of a separate address space
		for M88K .usr loads/stores.
20070520	Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
		Dnard, and Zaurus machine modes.
		Experimenting with dyntrans to_be_translated read-ahead. It
		seems to give a very small performance increase for MIPS
		emulation, but a large performance degradation for SuperH. Hm.
20070522	Disabling correct SuperH ITLB emulation; it does not seem to be
		necessary in order to let SH4 guest OSes run, and it slows down
		userspace code.
		Implementing "samepage" branches for SuperH emulation, and some
		other minor speed hacks.
20070525	Continuing on M88K memory-related stuff: exceptions, memory
		transaction register contents, etc.
		Implementing the M88K subu.ci instruction.
		Removing the non-working (skeleton) Iyonix machine mode.
		OpenBSD/mvme88k reaches userland :-), starts executing
		/sbin/init's instructions, and issues a few syscalls, before
		crashing.
20070526	Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
		the correct time-of-day.
		Implementing a generic IRQ controller for the test machines
		(dev_irqc), similar to a proposed patch from Petr Stepan.
		Experimenting some more with translation read-ahead.
		Adding an "expect" script for automated OpenBSD/landisk
		install regression/performance tests.
20070527	Adding a dummy mmEye (SH3) machine mode skeleton.
		FINALLY found the strange M88K bug I have been hunting: I had
		not emulated the SNIP value for exceptions occurring in
		branch delay slots correctly.
		Implementing correct exceptions for 64-bit M88K loads/stores.
		Address to symbol lookups are now disabled when M88K is
		running in usermode (because usermode addresses don't have
		anything to do with supervisor addresses).
20070531	Removing the mmEye machine mode skeleton.
20070604	Some minor code cleanup.
20070605	Moving src/useremul.c into a subdir (src/useremul/), and
		cleaning up some more legacy constructs.
		Adding -Wstrict-aliasing and -fstrict-aliasing detection to
		the configure script.
20070606	Adding a check for broken GCC on Solaris to the configure
		script. (GCC 3.4.3 on Solaris cannot handle static variables
		which are initialized to 0 or NULL. :-/)
		Removing the old (non-working) ARC emulation modes: NEC RD94,
		R94, R96, and R98, and the last traces of Olivetti M700 and
		Deskstation Tyne.
		Removing the non-working skeleton WDSC device (dev_wdsc).
20070607	Thinking about how to use the host's cc + ld at runtime to
		generate native code. (See experiments/native_cc_ld_test.i
		for an example.)
20070608	Adding a program counter sampling timer, which could be useful
		for native code generation experiments.
		The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
		should always be set, to allow a 5000/200 PROM to boot.
20070609	Moving out breakpoint details from the machine struct into
		a helper struct, and removing the limit on max nr of
		breakpoints.
20070610	Moving out tick functions into a helper struct as well (which
		also gets rid of the max limit).
20070612	FINALLY figured out why Debian/DECstation stopped working when
		translation read-ahead was enabled: in src/memory_rw.c, the
		call to invalidate_code_translation was made also if the
		memory access was an instruction load (if the page was mapped
		as writable); it shouldn't be called in that case.
20070613	Implementing some more MIPS32/64 revision 2 instructions: di,
		ei, ext, dext, dextm, dextu, and ins.
20070614	Implementing an instruction combination for the NetBSD/arm
		idle loop (making the host not use any cpu if NetBSD/arm
		inside the emulator is not using any cpu).
		Increasing the nr of ARM VPH entries from 128 to 384.
20070615	Removing the ENABLE_arch stuff from the configure script, so
		that all included architectures are included in both release
		and development builds.
		Moving memory related helper functions from misc.c to memory.c.
		Adding preliminary instructions for netbooting NetBSD/pmppc to
		guestoses.html; it doesn't work yet, there are weird timeouts.
		Beginning a total rewrite of the userland emulation modes
		(removing all emulation modes, beginning from scratch with
		NetBSD/MIPS and FreeBSD/Alpha only).
20070616	After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
		only cleared for the last segment when transmitting, not all
		segments), NetBSD/pmppc boots with root-on-nfs without the
		timeouts. Updating guestoses.html.
		Removing the skeleton PSP (Playstation Portable) mode.
		Moving X11-related stuff in the machine struct into a helper
		struct.
		Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
		macro (which prints a meaningful error message).
		Adding a COMMENT to each machine and device (for automagic
		.index comment generation).
		Doing regression testing for the next release.

==============  RELEASE 0.4.6  ==============
1 #ifndef CPU_M88K_H
2 #define CPU_M88K_H
3
4 /*
5 * Copyright (C) 2007 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cpu_m88k.h,v 1.21 2007/06/07 15:36:24 debug Exp $
32 */
33
34 #include "misc.h"
35 #include "interrupt.h"
36
37 #include "m88k_psl.h"
38
39 struct cpu_family;
40 struct timer;
41
42 /* M88K CPU types: */
43 struct m88k_cpu_type_def {
44 char *name;
45 int type;
46 uint32_t pid;
47 };
48
49 #define M88K_PID(arn,vn) ((arn << M88K_ARN_SHIFT) | (vn << M88K_VN_SHIFT))
50
51 #define M88K_CPU_TYPE_DEFS { \
52 { "88100", 88100, M88K_PID(M88K_ARN_88100,3) }, \
53 { "88110", 88110, M88K_PID(M88K_ARN_88110,0) }, \
54 { NULL, 0, 0 } \
55 }
56
57 /* Control register names: */
58 #define N_M88K_CONTROL_REGS 64
59 #define M88K_CR_NAMES { \
60 "PID", "PSR", "EPSR", "SSBR", /* 0 .. 3 */ \
61 "SXIP", "SNIP", "SFIP", "VBR", /* 4 .. 7 */ \
62 "DMT0", "DMD0", "DMA0", "DMT1", /* 8 .. 11 */ \
63 "DMD1", "DMA1", "DMT2", "DMD2", /* 12 .. 15 */ \
64 "DMA2", "SR0", "SR1", "SR2", /* 16 .. 19 */ \
65 "SR3", "CR21", "CR22", "CR23", /* 20 .. 23 */ \
66 "CR24", "CR25", "CR26", "CR27", /* 24 .. 27 */ \
67 "CR28", "CR29", "CR30", "CR31", /* 28 .. 31 */ \
68 "CR32", "CR33", "CR34", "CR35", /* 32 .. 35 */ \
69 "CR36", "CR37", "CR38", "CR39", /* 36 .. 39 */ \
70 "CR40", "CR41", "CR42", "CR43", /* 40 .. 43 */ \
71 "CR44", "CR45", "CR46", "CR47", /* 44 .. 47 */ \
72 "CR48", "CR49", "CR50", "CR51", /* 48 .. 51 */ \
73 "CR52", "CR53", "CR54", "CR55", /* 52 .. 55 */ \
74 "CR56", "CR57", "CR58", "CR59", /* 56 .. 59 */ \
75 "CR60", "CR61", "CR62", "CR63" /* 60 .. 63 */ }
76
77 #define M88K_CR_PID 0
78 #define M88K_CR_PSR 1
79 #define M88K_CR_EPSR 2
80 #define M88K_CR_SSBR 3
81 #define M88K_CR_SXIP 4
82 #define M88K_CR_SNIP 5
83 #define M88K_CR_SFIP 6
84 #define M88K_CR_VBR 7
85 #define M88K_CR_DMT0 8
86 #define M88K_CR_DMD0 9
87 #define M88K_CR_DMA0 10
88 #define M88K_CR_DMT1 11
89 #define M88K_CR_DMD1 12
90 #define M88K_CR_DMA1 13
91 #define M88K_CR_DMT2 14
92 #define M88K_CR_DMD2 15
93 #define M88K_CR_DMA2 16
94 #define M88K_CR_SR0 17
95 #define M88K_CR_SR1 18
96 #define M88K_CR_SR2 19
97 #define M88K_CR_SR3 20
98
99 /* MVME197 extended control registers: */
100 #define M88K_CR_NAMES_197 { \
101 "PID", "PSR", "EPSR", "SSBR", /* 0 .. 3 */ \
102 "EXIP", "ENIP", "SFIP", "VBR", /* 4 .. 7 */ \
103 "DMT0", "DMD0", "DMA0", "DMT1", /* 8 .. 11 */ \
104 "DMD1", "DMA1", "DMT2", "DMD2", /* 12 .. 15 */ \
105 "SRX", "SR0", "SR1", "SR2", /* 16 .. 19 */ \
106 "SR3", "CR21", "CR22", "CR23", /* 20 .. 23 */ \
107 "CR24", "ICMD", "ICTL", "ISAR", /* 24 .. 27 */ \
108 "ISAP", "IUAP", "IIR", "IBP", /* 28 .. 31 */ \
109 "IPPU", "IPPL", "ISR", "ILAR", /* 32 .. 35 */ \
110 "IPAR", "CR37", "CR38", "CR39", /* 36 .. 39 */ \
111 "DCMD", "DCTL", "DSAR", "DSAP", /* 40 .. 43 */ \
112 "DUAP", "DIR", "DBP", "DPPU", /* 44 .. 47 */ \
113 "DPPL", "DSR", "DLAR", "DPAR", /* 48 .. 51 */ \
114 "CR52", "CR53", "CR54", "CR55", /* 52 .. 55 */ \
115 "CR56", "CR57", "CR58", "CR59", /* 56 .. 59 */ \
116 "CR60", "CR61", "CR62", "CR63" /* 60 .. 63 */ }
117
118 #define M88K_CR_EXIP 4
119 #define M88K_CR_ENIP 5
120 #define M88K_CR_SRX 16
121 #define M88K_CR_ICMD 25
122 #define M88K_CR_ICTL 26
123 #define M88K_CR_ISAR 27
124 #define M88K_CR_ISAP 28
125 #define M88K_CR_IUAP 29
126 #define M88K_CR_IIR 30
127 #define M88K_CR_IBP 31
128 #define M88K_CR_IPPU 32
129 #define M88K_CR_IPPL 33
130 #define M88K_CR_ISR 34
131 #define M88K_CR_ILAR 35
132 #define M88K_CR_IPAR 36
133 #define M88K_CR_DCMD 40
134 #define M88K_CR_DCTL 41
135 #define M88K_CR_DSAR 42
136 #define M88K_CR_DSAP 43
137 #define M88K_CR_DUAP 44
138 #define M88K_CR_DIR 45
139 #define M88K_CR_DBP 46
140 #define M88K_CR_DPPU 47
141 #define M88K_CR_DPPL 48
142 #define M88K_CR_DSR 49
143 #define M88K_CR_DLAR 50
144 #define M88K_CR_DPAR 51
145
146 #define N_M88K_FPU_CONTROL_REGS 64
147
148
149 #define M88K_N_IC_ARGS 3
150 #define M88K_INSTR_ALIGNMENT_SHIFT 2
151 #define M88K_IC_ENTRIES_SHIFT 10
152 #define M88K_IC_ENTRIES_PER_PAGE (1 << M88K_IC_ENTRIES_SHIFT)
153 #define M88K_PC_TO_IC_ENTRY(a) (((a)>>M88K_INSTR_ALIGNMENT_SHIFT) \
154 & (M88K_IC_ENTRIES_PER_PAGE-1))
155 #define M88K_ADDR_TO_PAGENR(a) ((a) >> (M88K_IC_ENTRIES_SHIFT \
156 + M88K_INSTR_ALIGNMENT_SHIFT))
157
158 DYNTRANS_MISC_DECLARATIONS(m88k,M88K,uint32_t)
159
160 #define M88K_MAX_VPH_TLB_ENTRIES 128
161
162
163 #define N_M88K_REGS 32
164
165 /* Register r0 is always zero, r1 is the return address on function calls. */
166 #define M88K_ZERO_REG 0
167 #define M88K_RETURN_REG 1
168
169 #define M88K_CMP_HS 0x00000800
170 #define M88K_CMP_LO 0x00000400
171 #define M88K_CMP_LS 0x00000200
172 #define M88K_CMP_HI 0x00000100
173 #define M88K_CMP_GE 0x00000080
174 #define M88K_CMP_LT 0x00000040
175 #define M88K_CMP_LE 0x00000020
176 #define M88K_CMP_GT 0x00000010
177 #define M88K_CMP_NE 0x00000008
178 #define M88K_CMP_EQ 0x00000004
179
180 /* Exception numbers: */
181 #define M88K_EXCEPTION_RESET 0
182 #define M88K_EXCEPTION_INTERRUPT 1
183 #define M88K_EXCEPTION_INSTRUCTION_ACCESS 2
184 #define M88K_EXCEPTION_DATA_ACCESS 3
185 #define M88K_EXCEPTION_MISALIGNED_ACCESS 4
186 #define M88K_EXCEPTION_UNIMPLEMENTED_OPCODE 5
187 #define M88K_EXCEPTION_PRIVILEGE_VIOLATION 6
188 #define M88K_EXCEPTION_BOUNDS_CHECK_VIOLATION 7
189 #define M88K_EXCEPTION_ILLEGAL_INTEGER_DIVIDE 8
190 #define M88K_EXCEPTION_INTEGER_OVERFLOW 9
191 #define M88K_EXCEPTION_ERROR 10
192 #define M88K_EXCEPTION_SFU1_PRECISE 114
193 #define M88K_EXCEPTION_SFU1_IMPRECISE 115
194 #define M88K_EXCEPTION_USER_TRAPS_START 128
195
196 /* A reserved/unimplemented instruction, used for PROM calls: */
197 #define M88K_PROM_INSTR 0xf400fc92
198
199
200 /*
201 * M88200/88204 CMMU:
202 */
203
204 #define MAX_M8820X_CMMUS 8
205 #define M8820X_LENGTH 0x1000
206 #define N_M88200_BATC_REGS 10
207 #define N_M88200_PATC_ENTRIES 56
208 #define M8820X_PATC_SUPERVISOR_BIT 0x00000001
209
210 struct m8820x_cmmu {
211 uint32_t reg[M8820X_LENGTH / sizeof(uint32_t)];
212 uint32_t batc[N_M88200_BATC_REGS];
213 uint32_t patc_v_and_control[N_M88200_PATC_ENTRIES];
214 uint32_t patc_p_and_supervisorbit[N_M88200_PATC_ENTRIES];
215 int patc_update_index;
216 };
217
218
219 struct m88k_cpu {
220 struct m88k_cpu_type_def cpu_type;
221
222 /*
223 * General-Purpose Registers:
224 *
225 * 32 (N_M88K_REGS) registers, plus one which is always zero. (This
226 * is to support st.d with d = r31. ld.d with d=r31 is converted to
227 * just ld. TODO)
228 */
229 uint32_t r[N_M88K_REGS+1];
230
231 /* Destination scratch register for non-nop instructions with d=r0: */
232 uint32_t zero_scratch;
233
234 /* Control Registers: */
235 uint32_t cr[N_M88K_CONTROL_REGS];
236
237 /* Floating Point registers: */
238 uint32_t fcr[N_M88K_FPU_CONTROL_REGS];
239
240 /* Current interrupt assertion: */
241 int irq_asserted;
242
243 /* CMMUs (Cache/Memory Management Units): */
244 struct m8820x_cmmu *cmmu[MAX_M8820X_CMMUS];
245
246 /* Current memory transaction fault registers: */
247 uint32_t dmt[2];
248 uint32_t dmd[2];
249 uint32_t dma[2];
250
251 /* Delayed-branch target (for exception handling): */
252 uint32_t delay_target;
253
254
255 /*
256 * Instruction translation cache, internal TLB structure, and 32-bit
257 * virtual -> physical -> host address translation arrays for both
258 * normal access and for the special .usr access mode (available in
259 * supervisor mode).
260 */
261 DYNTRANS_ITC(m88k)
262 VPH_TLBS(m88k,M88K)
263 VPH32(m88k,M88K)
264 VPH32EXTENDED(m88k,M88K,usr)
265 };
266
267
268 /* cpu_m88k.c: */
269 int m88k_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
270 int m88k_run_instr(struct cpu *cpu);
271 void m88k_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
272 unsigned char *host_page, int writeflag, uint64_t paddr_page);
273 void m88k_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
274 void m88k_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
275 void m88k_timer_sample_tick(struct timer *, void *);
276 int m88k_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
277 unsigned char *data, size_t len, int writeflag, int cache_flags);
278 int m88k_cpu_family_init(struct cpu_family *);
279 void m88k_ldcr(struct cpu *cpu, uint32_t *r32ptr, int cr);
280 void m88k_stcr(struct cpu *cpu, uint32_t value, int cr, int rte);
281 void m88k_fstcr(struct cpu *cpu, uint32_t value, int fcr);
282 void m88k_exception(struct cpu *cpu, int vector, int is_trap);
283
284 /* memory_m88k.c: */
285 int m88k_translate_v2p(struct cpu *cpu, uint64_t vaddr,
286 uint64_t *return_addr, int flags);
287
288
289 #endif /* CPU_M88K_H */
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