src/include/cpu_ia64.h

#ifndef CPU_IA64_H
#define CPU_IA64_H

/*
 *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_ia64.h,v 1.3 2005/08/28 20:16:24 debug Exp $
 */

#include "misc.h"


struct cpu_family;

#define IA64_N_IC_ARGS                  3
#define IA64_INSTR_ALIGNMENT_SHIFT      4
#define IA64_IC_ENTRIES_SHIFT           8
#define IA64_IC_ENTRIES_PER_PAGE        (1 << IA64_IC_ENTRIES_SHIFT)
#define IA64_PC_TO_IC_ENTRY(a)          (((a)>>IA64_INSTR_ALIGNMENT_SHIFT) \
                                        & (IA64_IC_ENTRIES_PER_PAGE-1))
#define IA64_ADDR_TO_PAGENR(a)          ((a) >> (IA64_IC_ENTRIES_SHIFT \
                                        + IA64_INSTR_ALIGNMENT_SHIFT))

/*  TODO  */
struct ia64_instr_call {
        void    (*f)(struct cpu *, struct ia64_instr_call *);
        size_t  arg[IA64_N_IC_ARGS];
};

/*  Translation cache struct for each physical page:  */
struct ia64_tc_physpage {
        uint32_t        next_ofs;       /*  or 0 for end of chain  */
        uint32_t        physaddr;
        int             flags;
        struct ia64_instr_call ics[IA64_IC_ENTRIES_PER_PAGE + 1];
};


/*
 *  Virtual->physical->host page entry:
 *
 *      38 + 14 + 12 bits = 64 bits
 *
 *  TODO!!!!
 */
#define IA64_LEVEL0_SHIFT               26
#define IA64_LEVEL0                     8192
#define IA64_LEVEL1_SHIFT               12
#define IA64_LEVEL1                     16384
struct ia64_vph_page {
        void            *host_load[IA64_LEVEL1];
        void            *host_store[IA64_LEVEL1];
        uint64_t        phys_addr[IA64_LEVEL1];
        struct ia64_tc_physpage *phys_page[IA64_LEVEL1];
        int             refcount;
        struct ia64_vph_page    *next;  /*  Freelist, used if refcount = 0.  */
};


#define IA64_MAX_VPH_TLB_ENTRIES        48
struct ia64_vpg_tlb_entry {
        int             valid;
        int             writeflag;
        int64_t         timestamp;
        unsigned char   *host_page;
        uint64_t        vaddr_page;
        uint64_t        paddr_page;
};

struct ia64_cpu {
        /*  TODO  */
        uint64_t        r[128];


        /*
         *  Instruction translation cache:
         */

        /*  cur_ic_page is a pointer to an array of IA64_IC_ENTRIES_PER_PAGE
            instruction call entries. next_ic points to the next such
            call to be executed.  */
        struct ia64_tc_physpage *cur_physpage;
        struct ia64_instr_call  *cur_ic_page;
        struct ia64_instr_call  *next_ic;


        /*
         *  Virtual -> physical -> host address translation:
         */
        struct ia64_vpg_tlb_entry vph_tlb_entry[IA64_MAX_VPH_TLB_ENTRIES];
        struct ia64_vph_page    *vph_default_page;
        struct ia64_vph_page    *vph_next_free_page;
        struct ia64_vph_table   *vph_next_free_table;
        struct ia64_vph_page    *vph_table0[IA64_LEVEL0];
        struct ia64_vph_page    *vph_table0_kernel[IA64_LEVEL0];
};


/*  cpu_ia64.c:  */
void ia64_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void ia64_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int);
void ia64_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
int ia64_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
        unsigned char *data, size_t len, int writeflag, int cache_flags);
int ia64_userland_memory_rw(struct cpu *cpu, struct memory *mem,
        uint64_t vaddr, unsigned char *data, size_t len, int writeflag,
        int cache_flags);
int ia64_cpu_family_init(struct cpu_family *);


#endif  /*  CPU_IA64_H  */
1	#ifndef CPU_IA64_H
2	#define CPU_IA64_H
3
4	/*
5	* Copyright (C) 2005 Anders Gavare. All rights reserved.
6	*
7	* Redistribution and use in source and binary forms, with or without
8	* modification, are permitted provided that the following conditions are met:
9	*
10	* 1. Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	* 3. The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28	* SUCH DAMAGE.
29	*
30	*
31	* $Id: cpu_ia64.h,v 1.3 2005/08/28 20:16:24 debug Exp $
32	*/
33
34	#include "misc.h"
35
36
37	struct cpu_family;
38
39	#define IA64_N_IC_ARGS 3
40	#define IA64_INSTR_ALIGNMENT_SHIFT 4
41	#define IA64_IC_ENTRIES_SHIFT 8
42	#define IA64_IC_ENTRIES_PER_PAGE (1 << IA64_IC_ENTRIES_SHIFT)
43	#define IA64_PC_TO_IC_ENTRY(a) (((a)>>IA64_INSTR_ALIGNMENT_SHIFT) \
44	& (IA64_IC_ENTRIES_PER_PAGE-1))
45	#define IA64_ADDR_TO_PAGENR(a) ((a) >> (IA64_IC_ENTRIES_SHIFT \
46	+ IA64_INSTR_ALIGNMENT_SHIFT))
47
48	/* TODO */
49	struct ia64_instr_call {
50	void (f)(struct cpu , struct ia64_instr_call *);
51	size_t arg[IA64_N_IC_ARGS];
52	};
53
54	/* Translation cache struct for each physical page: */
55	struct ia64_tc_physpage {
56	uint32_t next_ofs; /* or 0 for end of chain */
57	uint32_t physaddr;
58	int flags;
59	struct ia64_instr_call ics[IA64_IC_ENTRIES_PER_PAGE + 1];
60	};
61
62
63	/*
64	* Virtual->physical->host page entry:
65	*
66	* 38 + 14 + 12 bits = 64 bits
67	*
68	* TODO!!!!
69	*/
70	#define IA64_LEVEL0_SHIFT 26
71	#define IA64_LEVEL0 8192
72	#define IA64_LEVEL1_SHIFT 12
73	#define IA64_LEVEL1 16384
74	struct ia64_vph_page {
75	void *host_load[IA64_LEVEL1];
76	void *host_store[IA64_LEVEL1];
77	uint64_t phys_addr[IA64_LEVEL1];
78	struct ia64_tc_physpage *phys_page[IA64_LEVEL1];
79	int refcount;
80	struct ia64_vph_page next; / Freelist, used if refcount = 0. */
81	};
82
83
84	#define IA64_MAX_VPH_TLB_ENTRIES 48
85	struct ia64_vpg_tlb_entry {
86	int valid;
87	int writeflag;
88	int64_t timestamp;
89	unsigned char *host_page;
90	uint64_t vaddr_page;
91	uint64_t paddr_page;
92	};
93
94	struct ia64_cpu {
95	/* TODO */
96	uint64_t r[128];
97
98
99	/*
100	* Instruction translation cache:
101	*/
102
103	/* cur_ic_page is a pointer to an array of IA64_IC_ENTRIES_PER_PAGE
104	instruction call entries. next_ic points to the next such
105	call to be executed. */
106	struct ia64_tc_physpage *cur_physpage;
107	struct ia64_instr_call *cur_ic_page;
108	struct ia64_instr_call *next_ic;
109
110
111	/*
112	* Virtual -> physical -> host address translation:
113	*/
114	struct ia64_vpg_tlb_entry vph_tlb_entry[IA64_MAX_VPH_TLB_ENTRIES];
115	struct ia64_vph_page *vph_default_page;
116	struct ia64_vph_page *vph_next_free_page;
117	struct ia64_vph_table *vph_next_free_table;
118	struct ia64_vph_page *vph_table0[IA64_LEVEL0];
119	struct ia64_vph_page *vph_table0_kernel[IA64_LEVEL0];
120	};
121
122
123	/* cpu_ia64.c: */
124	void ia64_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
125	unsigned char *host_page, int writeflag, uint64_t paddr_page);
126	void ia64_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int);
127	void ia64_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
128	int ia64_memory_rw(struct cpu cpu, struct memory mem, uint64_t vaddr,
129	unsigned char *data, size_t len, int writeflag, int cache_flags);
130	int ia64_userland_memory_rw(struct cpu cpu, struct memory mem,
131	uint64_t vaddr, unsigned char *data, size_t len, int writeflag,
132	int cache_flags);
133	int ia64_cpu_family_init(struct cpu_family *);
134
135
136	#endif /* CPU_IA64_H */