/[gxemul]/trunk/src/include/cpu_ia64.h
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Annotation of /trunk/src/include/cpu_ia64.h

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Revision 18 - (hide annotations)
Mon Oct 8 16:19:11 2007 UTC (13 years, 3 months ago) by dpavlin
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File size: 4468 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1004 2005/10/27 14:01:10 debug Exp $
20051011        Passing -A as the default boot arg for CATS (works fine with
                OpenBSD/cats).
20051012	Fixing the VGA cursor offset bug, and speeding up framebuffer
		redraws if character cells contain the same thing as during
		the last redraw.
20051013	Adding a slow strd ARM instruction hack.
20051017	Minor updates: Adding a dummy i80321 Verde controller (for
		XScale emulation), fixing the disassembly of the ARM "ldrd"
		instruction, adding "support" for less-than-4KB pages for ARM
		(by not adding them to translation tables).
20051020	Continuing on some HPCarm stuff. A NetBSD/hpcarm kernel prints
		some boot messages on an emulated Jornada 720.
		Making dev_ram work better with dyntrans (speeds up some things
		quite a bit).
20051021	Automatically generating some of the most common ARM load/store
		multiple instructions.
20051022	Better statistics gathering for the ARM load/store multiple.
		Various other dyntrans and device updates.
20051023	Various minor updates.
20051024	Continuing; minor device and dyntrans fine-tuning. Adding the
		first "reasonable" instruction combination hacks for ARM (the
		cores of NetBSD/cats' memset and memcpy).
20051025	Fixing a dyntrans-related bug in dev_vga. Also changing the
		dyntrans low/high access notification to only be updated on
		writes, not reads. Hopefully it will be enough. (dev_vga in
		charcell mode now seems to work correctly with both reads and
		writes.)
		Experimenting with gathering dyntrans statistics (which parts
		of emulated RAM that are actually executed), and adding
		instruction combination hacks for cache cleaning and a part of
		NetBSD's scanc() function.
20051026	Adding a bitmap for ARM emulation which indicates if a page is
		(specifically) user accessible; loads and stores with the t-
		flag set can now use the translation arrays, which results in
		a measurable speedup.
20051027	Dyntrans updates; adding an extra bitmap array for 32-bit
		emulation modes, speeding up the check whether a physical page
		has any code translations or not (O(n) -> O(1)). Doing a
		similar reduction of O(n) to O(1) by avoiding the scan through
		the translation entries on a translation update (32-bit mode
		only).
		Various other minor hacks.
20051029	Quick release, without any testing at all.

==============  RELEASE 0.3.6.2  ==============


1 dpavlin 12 #ifndef CPU_IA64_H
2     #define CPU_IA64_H
3    
4     /*
5     * Copyright (C) 2005 Anders Gavare. All rights reserved.
6     *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31 dpavlin 18 * $Id: cpu_ia64.h,v 1.5 2005/10/22 17:24:22 debug Exp $
32 dpavlin 12 */
33    
34     #include "misc.h"
35    
36    
37     struct cpu_family;
38    
39     #define IA64_N_IC_ARGS 3
40     #define IA64_INSTR_ALIGNMENT_SHIFT 4
41     #define IA64_IC_ENTRIES_SHIFT 8
42     #define IA64_IC_ENTRIES_PER_PAGE (1 << IA64_IC_ENTRIES_SHIFT)
43     #define IA64_PC_TO_IC_ENTRY(a) (((a)>>IA64_INSTR_ALIGNMENT_SHIFT) \
44     & (IA64_IC_ENTRIES_PER_PAGE-1))
45     #define IA64_ADDR_TO_PAGENR(a) ((a) >> (IA64_IC_ENTRIES_SHIFT \
46     + IA64_INSTR_ALIGNMENT_SHIFT))
47    
48     /* TODO */
49     struct ia64_instr_call {
50     void (*f)(struct cpu *, struct ia64_instr_call *);
51     size_t arg[IA64_N_IC_ARGS];
52     };
53    
54     /* Translation cache struct for each physical page: */
55     struct ia64_tc_physpage {
56 dpavlin 18 struct ia64_instr_call ics[IA64_IC_ENTRIES_PER_PAGE + 1];
57 dpavlin 12 uint32_t next_ofs; /* or 0 for end of chain */
58     int flags;
59 dpavlin 18 uint64_t physaddr;
60 dpavlin 12 };
61    
62    
63     /*
64     * Virtual->physical->host page entry:
65     *
66     * 38 + 14 + 12 bits = 64 bits
67     *
68     * TODO!!!!
69     */
70     #define IA64_LEVEL0_SHIFT 26
71     #define IA64_LEVEL0 8192
72     #define IA64_LEVEL1_SHIFT 12
73     #define IA64_LEVEL1 16384
74     struct ia64_vph_page {
75     void *host_load[IA64_LEVEL1];
76     void *host_store[IA64_LEVEL1];
77     uint64_t phys_addr[IA64_LEVEL1];
78     struct ia64_tc_physpage *phys_page[IA64_LEVEL1];
79     int refcount;
80     struct ia64_vph_page *next; /* Freelist, used if refcount = 0. */
81     };
82    
83    
84     #define IA64_MAX_VPH_TLB_ENTRIES 48
85     struct ia64_vpg_tlb_entry {
86     int valid;
87     int writeflag;
88     int64_t timestamp;
89     unsigned char *host_page;
90     uint64_t vaddr_page;
91     uint64_t paddr_page;
92     };
93    
94     struct ia64_cpu {
95     /* TODO */
96     uint64_t r[128];
97    
98    
99     /*
100     * Instruction translation cache:
101     */
102    
103     /* cur_ic_page is a pointer to an array of IA64_IC_ENTRIES_PER_PAGE
104     instruction call entries. next_ic points to the next such
105     call to be executed. */
106     struct ia64_tc_physpage *cur_physpage;
107     struct ia64_instr_call *cur_ic_page;
108     struct ia64_instr_call *next_ic;
109    
110    
111     /*
112     * Virtual -> physical -> host address translation:
113     */
114     struct ia64_vpg_tlb_entry vph_tlb_entry[IA64_MAX_VPH_TLB_ENTRIES];
115     struct ia64_vph_page *vph_default_page;
116     struct ia64_vph_page *vph_next_free_page;
117     struct ia64_vph_table *vph_next_free_table;
118     struct ia64_vph_page *vph_table0[IA64_LEVEL0];
119     struct ia64_vph_page *vph_table0_kernel[IA64_LEVEL0];
120     };
121    
122    
123     /* cpu_ia64.c: */
124     void ia64_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
125     unsigned char *host_page, int writeflag, uint64_t paddr_page);
126 dpavlin 18 void ia64_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
127 dpavlin 14 void ia64_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
128 dpavlin 12 int ia64_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
129     unsigned char *data, size_t len, int writeflag, int cache_flags);
130     int ia64_userland_memory_rw(struct cpu *cpu, struct memory *mem,
131     uint64_t vaddr, unsigned char *data, size_t len, int writeflag,
132     int cache_flags);
133     int ia64_cpu_family_init(struct cpu_family *);
134    
135    
136     #endif /* CPU_IA64_H */

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