Parent Directory | Revision Log
++ trunk/HISTORY (local) $Id: HISTORY,v 1.1055 2005/11/25 22:48:36 debug Exp $ 20051031 Adding disassembly support for more ARM instructions (clz, smul* etc), and adding a hack to support "new tiny" pages for StrongARM. 20051101 Minor documentation updates (NetBSD 2.0.2 -> 2.1, and OpenBSD 3.7 -> 3.8, and lots of testing). Changing from 1-sector PIO mode 0 transfers to 128-sector PIO mode 3 (in dev_wdc). Various minor ARM dyntrans updates (pc-relative loads from within the same page as the instruction are now treated as constant "mov"). 20051102 Re-enabling instruction combinations (they were accidentally disabled). Dyntrans TLB entries are now overwritten using a round-robin scheme instead of randomly. This increases performance. Fixing a typo in file.c (thanks to Chuan-Hua Chang for noticing it). Experimenting with adding ATAPI support to dev_wdc (to make emulated *BSD detect cdroms as cdroms, not harddisks). 20051104 Various minor updates. 20051105 Continuing on the ATAPI emulation. Seems to work well enough for a NetBSD/cats installation, but not OpenBSD/cats. Various other updates. 20051106 Modifying the -Y command line option to allow scaleup with certain graphic controllers (only dev_vga so far), not just scaledown. Some minor dyntrans cleanups. 20051107 Beginning a cleanup up the PCI subsystem (removing the read_register hack, etc). 20051108 Continuing the cleanup; splitting up some pci devices into a normal autodev device and some separate pci glue code. 20051109 Continuing on the PCI bus stuff; all old pci_*.c have been incorporated into normal devices and/or rewritten as glue code only, adding a dummy Intel 82371AB PIIX4 for Malta (not really tested yet). Minor pckbc fix so that Linux doesn't complain. Working on the DEC 21143 NIC (ethernet mac rom stuff mostly). Various other minor fixes. 20051110 Some more ARM dyntrans fine-tuning (e.g. some instruction combinations (cmps followed by conditional branch within the same page) and special cases for DPIs with regform when the shifter isn't used). 20051111 ARM dyntrans updates: O(n)->O(1) for just-mark-as-non- writable in the generic pc_to_pointers function, and some other minor hacks. Merging Cobalt and evbmips (Malta) ISA interrupt handling, and some minor fixes to allow Linux to accept harddisk irqs. 20051112 Minor device updates (pckbc, dec21143, lpt, ...), most importantly fixing the ALI M1543/M5229 so that harddisk irqs work with Linux/CATS. 20051113 Some more generalizations of the PCI subsystem. Finally took the time to add a hack for SCSI CDROM TOCs; this enables OpenBSD to use partition 'a' (as needed by the OpenBSD installer), and Windows NT's installer to get a bit further. Also fixing dev_wdc to allow Linux to detect ATAPI CDROMs. Continuing on the DEC 21143. 20051114 Minor ARM dyntrans tweaks; ARM cmps+branch optimization when comparing with 0, and generalizing the xchg instr. comb. Adding disassembly of ARM mrrc/mcrr and q{,d}{add,sub}. 20051115 Continuing on various PPC things (BATs, other address trans- lation things, various loads/stores, BeBox emulation, etc.). Beginning to work on PPC interrupt/exception support. 20051116 Factoring out some code which initializes legacy ISA devices from those machines that use them (bus_isa). Continuing on PPC interrupt/exception support. 20051117 Minor Malta fixes: RTC year offset = 80, disabling a speed hack which caused NetBSD to detect a too fast cpu, and adding a new hack to make Linux detect a faster cpu. Continuing on the Artesyn PM/PPC emulation mode. Adding an Algor emulation skeleton (P4032 and P5064); implementing some of the basics. Continuing on PPC emulation in general; usage of unimplemented SPRs is now easier to track, continuing on memory/exception related issues, etc. 20051118 More work on PPC emulation (tgpr0..3, exception handling, memory stuff, syscalls, etc.). 20051119 Changing the ARM dyntrans code to mostly use cpu->pc, and not necessarily use arm reg 15. Seems to work. Various PPC updates; continuing on the PReP emulation mode. 20051120 Adding a workaround/hack to dev_mc146818 to allow NetBSD/prep to detect the clock. 20051121 More cleanup of the PCI bus (memory and I/O bases, etc). Continuing on various PPC things (decrementer and timebase, WDCs on obio (on PReP) use irq 13, not 14/15). 20051122 Continuing on the CPC700 controller (interrupts etc) for PMPPC, and on PPC stuff in general. Finally! After some bug fixes to the virtual to physical addr translation, NetBSD/{prep,pmppc} 2.1 reach userland and are stable enough to be interacted with. More PCI updates; reverse-endian device access for PowerPC etc. 20051123 Generalizing the IEEE floating point subsystem (moving it out from src/cpus/cpu_mips_coproc.c into a new src/float_emul.c). Input via slave xterms was sometimes not really working; fixing this for ns16550, and a warning message is now displayed if multiple non-xterm consoles are active. Adding some PPC floating point support, etc. Various interrupt related updates (dev_wdc, _ns16550, _8259, and the isa32 common code in machine.c). NetBSD/prep can now be installed! :-) (Well, with some manual commands necessary before running sysinst.) Updating the documentation and various other things to reflect this. 20051124 Various minor documentation updates. Continuing the work on the DEC 21143 NIC. 20051125 LOTS of work on the 21143. Both OpenBSD and NetBSD work fine with it now, except that OpenBSD sometimes gives a time-out warning. Minor documentation updates. ============== RELEASE 0.3.7 ==============
1 | dpavlin | 14 | #ifndef CPU_HPPA_H |
2 | #define CPU_HPPA_H | ||
3 | |||
4 | /* | ||
5 | * Copyright (C) 2005 Anders Gavare. All rights reserved. | ||
6 | * | ||
7 | * Redistribution and use in source and binary forms, with or without | ||
8 | * modification, are permitted provided that the following conditions are met: | ||
9 | * | ||
10 | * 1. Redistributions of source code must retain the above copyright | ||
11 | * notice, this list of conditions and the following disclaimer. | ||
12 | * 2. Redistributions in binary form must reproduce the above copyright | ||
13 | * notice, this list of conditions and the following disclaimer in the | ||
14 | * documentation and/or other materials provided with the distribution. | ||
15 | * 3. The name of the author may not be used to endorse or promote products | ||
16 | * derived from this software without specific prior written permission. | ||
17 | * | ||
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND | ||
19 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | ||
20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
21 | dpavlin | 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
22 | dpavlin | 14 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | ||
24 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | ||
25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | ||
26 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | ||
27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | ||
28 | * SUCH DAMAGE. | ||
29 | * | ||
30 | * | ||
31 | dpavlin | 20 | * $Id: cpu_hppa.h,v 1.12 2005/11/16 21:15:19 debug Exp $ |
32 | dpavlin | 14 | */ |
33 | |||
34 | #include "misc.h" | ||
35 | |||
36 | |||
37 | struct cpu_family; | ||
38 | |||
39 | |||
40 | #define HPPA_N_IC_ARGS 3 | ||
41 | #define HPPA_INSTR_ALIGNMENT_SHIFT 2 | ||
42 | #define HPPA_IC_ENTRIES_SHIFT 10 | ||
43 | #define HPPA_IC_ENTRIES_PER_PAGE (1 << HPPA_IC_ENTRIES_SHIFT) | ||
44 | #define HPPA_PC_TO_IC_ENTRY(a) (((a)>>HPPA_INSTR_ALIGNMENT_SHIFT) \ | ||
45 | & (HPPA_IC_ENTRIES_PER_PAGE-1)) | ||
46 | #define HPPA_ADDR_TO_PAGENR(a) ((a) >> (HPPA_IC_ENTRIES_SHIFT \ | ||
47 | + HPPA_INSTR_ALIGNMENT_SHIFT)) | ||
48 | |||
49 | struct hppa_instr_call { | ||
50 | void (*f)(struct cpu *, struct hppa_instr_call *); | ||
51 | size_t arg[HPPA_N_IC_ARGS]; | ||
52 | }; | ||
53 | |||
54 | /* Translation cache struct for each physical page: */ | ||
55 | struct hppa_tc_physpage { | ||
56 | dpavlin | 18 | struct hppa_instr_call ics[HPPA_IC_ENTRIES_PER_PAGE + 1]; |
57 | dpavlin | 14 | uint32_t next_ofs; /* or 0 for end of chain */ |
58 | dpavlin | 18 | int flags; |
59 | dpavlin | 14 | uint64_t physaddr; |
60 | }; | ||
61 | |||
62 | #define HPPA_N_VPH_ENTRIES 1048576 | ||
63 | |||
64 | #define HPPA_MAX_VPH_TLB_ENTRIES 256 | ||
65 | struct hppa_vpg_tlb_entry { | ||
66 | dpavlin | 20 | unsigned char valid; |
67 | unsigned char writeflag; | ||
68 | dpavlin | 14 | int64_t timestamp; |
69 | uint64_t vaddr_page; | ||
70 | uint64_t paddr_page; | ||
71 | dpavlin | 20 | unsigned char *host_page; |
72 | dpavlin | 14 | }; |
73 | |||
74 | struct hppa_cpu { | ||
75 | int bits; /* 32 or 64 */ | ||
76 | |||
77 | uint64_t r[32]; | ||
78 | |||
79 | |||
80 | /* | ||
81 | * Instruction translation cache: | ||
82 | */ | ||
83 | |||
84 | /* cur_ic_page is a pointer to an array of HPPA_IC_ENTRIES_PER_PAGE | ||
85 | instruction call entries. next_ic points to the next such | ||
86 | call to be executed. */ | ||
87 | struct hppa_tc_physpage *cur_physpage; | ||
88 | struct hppa_instr_call *cur_ic_page; | ||
89 | struct hppa_instr_call *next_ic; | ||
90 | |||
91 | dpavlin | 20 | void (*combination_check)(struct cpu *, |
92 | struct hppa_instr_call *, int low_addr); | ||
93 | dpavlin | 14 | |
94 | /* | ||
95 | * Virtual -> physical -> host address translation: | ||
96 | * | ||
97 | * host_load and host_store point to arrays of HPPA_N_VPH_ENTRIES | ||
98 | * pointers (to host pages); phys_addr points to an array of | ||
99 | * HPPA_N_VPH_ENTRIES uint32_t. | ||
100 | */ | ||
101 | |||
102 | struct hppa_vpg_tlb_entry vph_tlb_entry[HPPA_MAX_VPH_TLB_ENTRIES]; | ||
103 | dpavlin | 18 | unsigned char *host_load[HPPA_N_VPH_ENTRIES]; |
104 | unsigned char *host_store[HPPA_N_VPH_ENTRIES]; | ||
105 | uint32_t phys_addr[HPPA_N_VPH_ENTRIES]; | ||
106 | dpavlin | 14 | struct hppa_tc_physpage *phys_page[HPPA_N_VPH_ENTRIES]; |
107 | dpavlin | 18 | |
108 | uint32_t phystranslation[HPPA_N_VPH_ENTRIES/32]; | ||
109 | dpavlin | 20 | uint8_t vaddr_to_tlbindex[HPPA_N_VPH_ENTRIES]; |
110 | dpavlin | 14 | }; |
111 | |||
112 | |||
113 | /* cpu_hppa.c: */ | ||
114 | void hppa_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, | ||
115 | unsigned char *host_page, int writeflag, uint64_t paddr_page); | ||
116 | dpavlin | 18 | void hppa_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
117 | dpavlin | 14 | void hppa_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
118 | void hppa32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, | ||
119 | unsigned char *host_page, int writeflag, uint64_t paddr_page); | ||
120 | dpavlin | 18 | void hppa32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
121 | dpavlin | 14 | void hppa32_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
122 | int hppa_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, | ||
123 | unsigned char *data, size_t len, int writeflag, int cache_flags); | ||
124 | int hppa_cpu_family_init(struct cpu_family *); | ||
125 | |||
126 | |||
127 | #endif /* CPU_HPPA_H */ |
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