/[gxemul]/trunk/src/include/cpu_hppa.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Annotation of /trunk/src/include/cpu_hppa.h

Parent Directory Parent Directory | Revision Log Revision Log

Revision 18 - (hide annotations)
Mon Oct 8 16:19:11 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 4382 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1004 2005/10/27 14:01:10 debug Exp $
20051011        Passing -A as the default boot arg for CATS (works fine with
                OpenBSD/cats).
20051012	Fixing the VGA cursor offset bug, and speeding up framebuffer
		redraws if character cells contain the same thing as during
		the last redraw.
20051013	Adding a slow strd ARM instruction hack.
20051017	Minor updates: Adding a dummy i80321 Verde controller (for
		XScale emulation), fixing the disassembly of the ARM "ldrd"
		instruction, adding "support" for less-than-4KB pages for ARM
		(by not adding them to translation tables).
20051020	Continuing on some HPCarm stuff. A NetBSD/hpcarm kernel prints
		some boot messages on an emulated Jornada 720.
		Making dev_ram work better with dyntrans (speeds up some things
		quite a bit).
20051021	Automatically generating some of the most common ARM load/store
		multiple instructions.
20051022	Better statistics gathering for the ARM load/store multiple.
		Various other dyntrans and device updates.
20051023	Various minor updates.
20051024	Continuing; minor device and dyntrans fine-tuning. Adding the
		first "reasonable" instruction combination hacks for ARM (the
		cores of NetBSD/cats' memset and memcpy).
20051025	Fixing a dyntrans-related bug in dev_vga. Also changing the
		dyntrans low/high access notification to only be updated on
		writes, not reads. Hopefully it will be enough. (dev_vga in
		charcell mode now seems to work correctly with both reads and
		writes.)
		Experimenting with gathering dyntrans statistics (which parts
		of emulated RAM that are actually executed), and adding
		instruction combination hacks for cache cleaning and a part of
		NetBSD's scanc() function.
20051026	Adding a bitmap for ARM emulation which indicates if a page is
		(specifically) user accessible; loads and stores with the t-
		flag set can now use the translation arrays, which results in
		a measurable speedup.
20051027	Dyntrans updates; adding an extra bitmap array for 32-bit
		emulation modes, speeding up the check whether a physical page
		has any code translations or not (O(n) -> O(1)). Doing a
		similar reduction of O(n) to O(1) by avoiding the scan through
		the translation entries on a translation update (32-bit mode
		only).
		Various other minor hacks.
20051029	Quick release, without any testing at all.

==============  RELEASE 0.3.6.2  ==============
1 dpavlin 14 #ifndef CPU_HPPA_H
2     #define CPU_HPPA_H
3    
4     /*
5     * Copyright (C) 2005 Anders Gavare. All rights reserved.
6     *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT HPPAALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31 dpavlin 18 * $Id: cpu_hppa.h,v 1.8 2005/10/27 14:01:15 debug Exp $
32 dpavlin 14 */
33    
34     #include "misc.h"
35    
36    
37     struct cpu_family;
38    
39    
40     #define HPPA_N_IC_ARGS 3
41     #define HPPA_INSTR_ALIGNMENT_SHIFT 2
42     #define HPPA_IC_ENTRIES_SHIFT 10
43     #define HPPA_IC_ENTRIES_PER_PAGE (1 << HPPA_IC_ENTRIES_SHIFT)
44     #define HPPA_PC_TO_IC_ENTRY(a) (((a)>>HPPA_INSTR_ALIGNMENT_SHIFT) \
45     & (HPPA_IC_ENTRIES_PER_PAGE-1))
46     #define HPPA_ADDR_TO_PAGENR(a) ((a) >> (HPPA_IC_ENTRIES_SHIFT \
47     + HPPA_INSTR_ALIGNMENT_SHIFT))
48    
49     struct hppa_instr_call {
50     void (*f)(struct cpu *, struct hppa_instr_call *);
51     size_t arg[HPPA_N_IC_ARGS];
52     };
53    
54     /* Translation cache struct for each physical page: */
55     struct hppa_tc_physpage {
56 dpavlin 18 struct hppa_instr_call ics[HPPA_IC_ENTRIES_PER_PAGE + 1];
57 dpavlin 14 uint32_t next_ofs; /* or 0 for end of chain */
58 dpavlin 18 int flags;
59 dpavlin 14 uint64_t physaddr;
60     };
61    
62     #define HPPA_N_VPH_ENTRIES 1048576
63    
64     #define HPPA_MAX_VPH_TLB_ENTRIES 256
65     struct hppa_vpg_tlb_entry {
66     int valid;
67     int writeflag;
68     int64_t timestamp;
69     unsigned char *host_page;
70     uint64_t vaddr_page;
71     uint64_t paddr_page;
72     };
73    
74     struct hppa_cpu {
75     int bits; /* 32 or 64 */
76    
77     uint64_t r[32];
78    
79    
80     /*
81     * Instruction translation cache:
82     */
83    
84     /* cur_ic_page is a pointer to an array of HPPA_IC_ENTRIES_PER_PAGE
85     instruction call entries. next_ic points to the next such
86     call to be executed. */
87     struct hppa_tc_physpage *cur_physpage;
88     struct hppa_instr_call *cur_ic_page;
89     struct hppa_instr_call *next_ic;
90    
91    
92     /*
93     * Virtual -> physical -> host address translation:
94     *
95     * host_load and host_store point to arrays of HPPA_N_VPH_ENTRIES
96     * pointers (to host pages); phys_addr points to an array of
97     * HPPA_N_VPH_ENTRIES uint32_t.
98     */
99    
100     struct hppa_vpg_tlb_entry vph_tlb_entry[HPPA_MAX_VPH_TLB_ENTRIES];
101 dpavlin 18 unsigned char *host_load[HPPA_N_VPH_ENTRIES];
102     unsigned char *host_store[HPPA_N_VPH_ENTRIES];
103     uint32_t phys_addr[HPPA_N_VPH_ENTRIES];
104 dpavlin 14 struct hppa_tc_physpage *phys_page[HPPA_N_VPH_ENTRIES];
105 dpavlin 18
106     uint32_t phystranslation[HPPA_N_VPH_ENTRIES/32];
107 dpavlin 14 };
108    
109    
110     /* cpu_hppa.c: */
111     void hppa_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
112     unsigned char *host_page, int writeflag, uint64_t paddr_page);
113 dpavlin 18 void hppa_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
114 dpavlin 14 void hppa_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
115     void hppa32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
116     unsigned char *host_page, int writeflag, uint64_t paddr_page);
117 dpavlin 18 void hppa32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
118 dpavlin 14 void hppa32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
119     int hppa_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
120     unsigned char *data, size_t len, int writeflag, int cache_flags);
121     int hppa_cpu_family_init(struct cpu_family *);
122    
123    
124     #endif /* CPU_HPPA_H */
  ViewVC Help
Powered by ViewVC 1.1.26