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#define CPU_AVR_H |
#define CPU_AVR_H |
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/* |
/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_avr.h,v 1.7 2005/10/27 14:01:15 debug Exp $ |
* $Id: cpu_avr.h,v 1.17 2006/07/16 13:32:27 debug Exp $ |
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*/ |
*/ |
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#include "misc.h" |
#include "misc.h" |
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#define N_AVR_REGS 32 |
#define N_AVR_REGS 32 |
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#define AVR_N_IC_ARGS 2 |
#define AVR_N_IC_ARGS 4 |
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#define AVR_INSTR_ALIGNMENT_SHIFT 1 |
#define AVR_INSTR_ALIGNMENT_SHIFT 1 |
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#define AVR_IC_ENTRIES_SHIFT 11 |
#define AVR_IC_ENTRIES_SHIFT 11 |
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#define AVR_IC_ENTRIES_PER_PAGE (1 << AVR_IC_ENTRIES_SHIFT) |
#define AVR_IC_ENTRIES_PER_PAGE (1 << AVR_IC_ENTRIES_SHIFT) |
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#define AVR_ADDR_TO_PAGENR(a) ((a) >> (AVR_IC_ENTRIES_SHIFT \ |
#define AVR_ADDR_TO_PAGENR(a) ((a) >> (AVR_IC_ENTRIES_SHIFT \ |
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+ AVR_INSTR_ALIGNMENT_SHIFT)) |
+ AVR_INSTR_ALIGNMENT_SHIFT)) |
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struct avr_instr_call { |
DYNTRANS_MISC_DECLARATIONS(avr,AVR,uint64_t) |
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void (*f)(struct cpu *, struct avr_instr_call *); |
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size_t arg[AVR_N_IC_ARGS]; |
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}; |
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/* Translation cache struct for each physical page: */ |
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struct avr_tc_physpage { |
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struct avr_instr_call ics[AVR_IC_ENTRIES_PER_PAGE + 1]; |
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uint32_t next_ofs; /* or 0 for end of chain */ |
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uint32_t physaddr; |
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int flags; |
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}; |
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#define AVR_MAX_VPH_TLB_ENTRIES 128 |
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#define AVR_N_VPH_ENTRIES 1048576 |
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#define AVR_MAX_VPH_TLB_ENTRIES 256 |
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struct avr_vpg_tlb_entry { |
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int valid; |
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int writeflag; |
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int64_t timestamp; |
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unsigned char *host_page; |
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uint32_t vaddr_page; |
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uint32_t paddr_page; |
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}; |
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#define SREG_NAMES "cznvshti" |
#define SREG_NAMES "cznvshti" |
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#define AVR_SREG_T 0x40 /* Transfer bit */ |
#define AVR_SREG_T 0x40 /* Transfer bit */ |
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#define AVR_SREG_I 0x80 /* Interrupt enable/disable */ |
#define AVR_SREG_I 0x80 /* Interrupt enable/disable */ |
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#define AVR_SRAM_BASE 0x800000 |
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struct avr_cpu { |
struct avr_cpu { |
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uint32_t pc_mask; |
uint32_t pc_mask; |
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int is_22bit; /* 0 for 16-bit, 1 for 22-bit PC */ |
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uint32_t sram_mask; |
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/* |
/* |
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* General Purpose Registers: |
* General Purpose Registers: |
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/* Status register: */ |
/* Status register: */ |
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uint8_t sreg; |
uint8_t sreg; |
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/* Ports A-D: */ |
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uint8_t ddra; /* Direction */ |
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uint8_t ddrb; |
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uint8_t ddrc; |
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uint8_t ddrd; |
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uint8_t porta_read; |
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uint8_t porta_write; |
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uint8_t portb_read; |
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uint8_t portb_write; |
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uint8_t portc_read; |
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uint8_t portc_write; |
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uint8_t portd_read; |
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uint8_t portd_write; |
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/* Stack pointer (high and low byte combined): */ |
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uint16_t sp; |
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/* |
/* |
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* In order to keep an accurate cycle count, this variable should be |
* In order to keep an accurate cycle count, this variable should be |
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* increased for those instructions that take longer than 1 cycle to |
* increased for those instructions that take longer than 1 cycle to |
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/* |
/* |
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* Instruction translation cache: |
* Instruction translation cache: |
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*/ |
*/ |
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DYNTRANS_ITC(avr) |
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/* cur_ic_page is a pointer to an array of AVR_IC_ENTRIES_PER_PAGE |
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instruction call entries. next_ic points to the next such |
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call to be executed. */ |
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struct avr_tc_physpage *cur_physpage; |
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struct avr_instr_call *cur_ic_page; |
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struct avr_instr_call *next_ic; |
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/* |
/* |
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* Virtual -> physical -> host address translation: |
* 32-bit virtual -> physical -> host address translation: |
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* |
* |
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* host_load and host_store point to arrays of AVR_N_VPH_ENTRIES |
* (All 32 bits are not really needed on AVRs.) |
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* pointers (to host pages); phys_addr points to an array of |
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* AVR_N_VPH_ENTRIES uint32_t. |
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*/ |
*/ |
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VPH_TLBS(avr,AVR) |
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struct avr_vpg_tlb_entry vph_tlb_entry[AVR_MAX_VPH_TLB_ENTRIES]; |
VPH32(avr,AVR,uint32_t,uint8_t) |
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unsigned char *host_load[AVR_N_VPH_ENTRIES]; |
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unsigned char *host_store[AVR_N_VPH_ENTRIES]; |
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uint32_t phys_addr[AVR_N_VPH_ENTRIES]; |
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struct avr_tc_physpage *phys_page[AVR_N_VPH_ENTRIES]; |
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uint32_t phystranslation[AVR_N_VPH_ENTRIES/32]; |
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}; |
}; |
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/* cpu_avr.c: */ |
/* cpu_avr.c: */ |
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int avr_run_instr(struct cpu *cpu); |
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void avr_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
void avr_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void avr_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
void avr_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |