/[gxemul]/trunk/src/include/cpu_avr.h
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Annotation of /trunk/src/include/cpu_avr.h

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Revision 28 - (hide annotations)
Mon Oct 8 16:20:26 2007 UTC (13 years, 3 months ago) by dpavlin
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File size: 4245 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $
20060626	Continuing on SPARC emulation (beginning on the 'save'
		instruction, register windows, etc).
20060629	Planning statistics gathering (new -s command line option),
		and renaming speed_tricks to allow_instruction_combinations.
20060630	Some minor manual page updates.
		Various cleanups.
		Implementing the -s command line option.
20060701	FINALLY found the bug which prevented Linux and Ultrix from
		running without the ugly hack in the R2000/R3000 cache isol
		code; it was the phystranslation hint array which was buggy.
		Removing the phystranslation hint code completely, for now.
20060702	Minor dyntrans cleanups; invalidation of physpages now only
		invalidate those parts of a page that have actually been
		translated. (32 parts per page.)
		Some MIPS non-R3000 speed fixes.
		Experimenting with MIPS instruction combination for some
		addiu+bne+sw loops, and sw+sw+sw.
		Adding support (again) for larger-than-4KB pages in MIPS tlbw*.
		Continuing on SPARC emulation: adding load/store instructions.
20060704	Fixing a virtual vs physical page shift bug in the new tlbw*
		implementation. Problem noticed by Jakub Jermar. (Many thanks.)
		Moving rfe and eret to cpu_mips_instr.c, since that is the
		only place that uses them nowadays.
20060705	Removing the BSD license from the "testmachine" include files,
		placing them in the public domain instead; this enables the
		testmachine stuff to be used from projects which are
		incompatible with the BSD license for some reason.
20060707	Adding instruction combinations for the R2000/R3000 L1
		I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu,
		various branches followed by addiu or nop, and jr ra followed
		by addiu. The time it takes to perform a full NetBSD/pmax R3000
		install on the laptop has dropped from 573 seconds to 539. :-)
20060708	Adding a framebuffer controller device (dev_fbctrl), which so
		far can be used to change the fb resolution during runtime, but
		in the future will also be useful for accelerated block fill/
		copy, and possibly also simplified character output.
		Adding an instruction combination for NetBSD/pmax' strlen.
20060709	Minor fixes: reading raw files in src/file.c wasn't memblock
		aligned, removing buggy multi_sw MIPS instruction combination,
		etc.
20060711	Adding a machine_qemu.c, which contains a "qemu_mips" machine.
		(It mimics QEMU's MIPS machine mode, so that a test kernel
		made for QEMU_MIPS also can run in GXemul... at least to some
		extent.)  Adding a short section about how to run this mode to
		doc/guestoses.html.
20060714	Misc. minor code cleanups.
20060715	Applying a patch which adds getchar() to promemul/yamon.c
		(from Oleksandr Tymoshenko).
		Adding yamon.h from NetBSD, and rewriting yamon.c to use it
		(instead of ugly hardcoded numbers) + some cleanup.
20060716	Found and fixed the bug which broke single-stepping of 64-bit
		programs between 0.4.0 and 0.4.0.1 (caused by too quick
		refactoring and no testing). Hopefully this fix will not
		break too many other things.
20060718	Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS.
		Re-adding the sw+sw+sw instr comb (the problem was that I had
		ignored endian issues); however, it doesn't seem to give any
		big performance gain.
20060720	Adding a dummy Transputer mode (T414, T800 etc) skeleton (only
		the 'j' and 'ldc' instructions are implemented so far). :-}
20060721	Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus
		misc. other updates to get Linux 2.6 for evbmips/malta working
		(thanks to Alec Voropay for the details).
		FINALLY found and fixed the bug which made tlbw* for non-R3000
		buggy; it was a reference count problem in the dyntrans core.
20060722	Testing stuff; things seem stable enough for a new release.

==============  RELEASE 0.4.1  ==============


1 dpavlin 14 #ifndef CPU_AVR_H
2     #define CPU_AVR_H
3    
4     /*
5 dpavlin 22 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
6 dpavlin 14 *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31 dpavlin 28 * $Id: cpu_avr.h,v 1.17 2006/07/16 13:32:27 debug Exp $
32 dpavlin 14 */
33    
34     #include "misc.h"
35    
36    
37     struct cpu_family;
38    
39     #define N_AVR_REGS 32
40    
41 dpavlin 24 #define AVR_N_IC_ARGS 4
42 dpavlin 14 #define AVR_INSTR_ALIGNMENT_SHIFT 1
43     #define AVR_IC_ENTRIES_SHIFT 11
44     #define AVR_IC_ENTRIES_PER_PAGE (1 << AVR_IC_ENTRIES_SHIFT)
45     #define AVR_PC_TO_IC_ENTRY(a) (((a)>>AVR_INSTR_ALIGNMENT_SHIFT) \
46     & (AVR_IC_ENTRIES_PER_PAGE-1))
47     #define AVR_ADDR_TO_PAGENR(a) ((a) >> (AVR_IC_ENTRIES_SHIFT \
48     + AVR_INSTR_ALIGNMENT_SHIFT))
49    
50 dpavlin 22 DYNTRANS_MISC_DECLARATIONS(avr,AVR,uint64_t)
51 dpavlin 14
52 dpavlin 22 #define AVR_MAX_VPH_TLB_ENTRIES 128
53 dpavlin 14
54    
55     #define SREG_NAMES "cznvshti"
56    
57     #define AVR_SREG_C 0x01 /* Carry flag */
58     #define AVR_SREG_Z 0x02 /* Zero flag */
59     #define AVR_SREG_N 0x04 /* Negative flag */
60     #define AVR_SREG_V 0x08 /* Overflow flag */
61     #define AVR_SREG_S 0x10 /* Signed test */
62     #define AVR_SREG_H 0x20 /* Half carry flag */
63     #define AVR_SREG_T 0x40 /* Transfer bit */
64     #define AVR_SREG_I 0x80 /* Interrupt enable/disable */
65    
66 dpavlin 24 #define AVR_SRAM_BASE 0x800000
67 dpavlin 14
68 dpavlin 24
69 dpavlin 14 struct avr_cpu {
70     uint32_t pc_mask;
71 dpavlin 24 int is_22bit; /* 0 for 16-bit, 1 for 22-bit PC */
72 dpavlin 14
73 dpavlin 24 uint32_t sram_mask;
74    
75 dpavlin 14 /*
76     * General Purpose Registers:
77     */
78     uint8_t r[N_AVR_REGS];
79    
80     /* Status register: */
81     uint8_t sreg;
82    
83 dpavlin 24 /* Ports A-D: */
84     uint8_t ddra; /* Direction */
85     uint8_t ddrb;
86     uint8_t ddrc;
87     uint8_t ddrd;
88     uint8_t porta_read;
89     uint8_t porta_write;
90     uint8_t portb_read;
91     uint8_t portb_write;
92     uint8_t portc_read;
93     uint8_t portc_write;
94     uint8_t portd_read;
95     uint8_t portd_write;
96    
97     /* Stack pointer (high and low byte combined): */
98     uint16_t sp;
99    
100 dpavlin 14 /*
101     * In order to keep an accurate cycle count, this variable should be
102     * increased for those instructions that take longer than 1 cycle to
103     * execute. The total number of executed cycles is extra_cycles PLUS
104     * the number of executed instructions.
105     */
106     int64_t extra_cycles;
107    
108    
109     /*
110     * Instruction translation cache:
111     */
112 dpavlin 22 DYNTRANS_ITC(avr)
113 dpavlin 14
114     /*
115 dpavlin 22 * 32-bit virtual -> physical -> host address translation:
116 dpavlin 14 *
117 dpavlin 22 * (All 32 bits are not really needed on AVRs.)
118 dpavlin 14 */
119 dpavlin 22 VPH_TLBS(avr,AVR)
120     VPH32(avr,AVR,uint32_t,uint8_t)
121 dpavlin 14 };
122    
123    
124     /* cpu_avr.c: */
125 dpavlin 28 int avr_run_instr(struct cpu *cpu);
126 dpavlin 14 void avr_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
127     unsigned char *host_page, int writeflag, uint64_t paddr_page);
128 dpavlin 18 void avr_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
129 dpavlin 14 void avr_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
130     int avr_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
131     unsigned char *data, size_t len, int writeflag, int cache_flags);
132     int avr_cpu_family_init(struct cpu_family *);
133    
134    
135     #endif /* CPU_AVR_H */

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