/[gxemul]/trunk/src/include/cpu_avr.h
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Annotation of /trunk/src/include/cpu_avr.h

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Mon Oct 8 16:19:37 2007 UTC (13 years, 3 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 dpavlin 14 #ifndef CPU_AVR_H
2     #define CPU_AVR_H
3    
4     /*
5 dpavlin 22 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
6 dpavlin 14 *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31 dpavlin 22 * $Id: cpu_avr.h,v 1.14 2006/02/09 22:40:27 debug Exp $
32 dpavlin 14 */
33    
34     #include "misc.h"
35    
36    
37     struct cpu_family;
38    
39     #define N_AVR_REGS 32
40    
41 dpavlin 22 #define AVR_N_IC_ARGS 3
42 dpavlin 14 #define AVR_INSTR_ALIGNMENT_SHIFT 1
43     #define AVR_IC_ENTRIES_SHIFT 11
44     #define AVR_IC_ENTRIES_PER_PAGE (1 << AVR_IC_ENTRIES_SHIFT)
45     #define AVR_PC_TO_IC_ENTRY(a) (((a)>>AVR_INSTR_ALIGNMENT_SHIFT) \
46     & (AVR_IC_ENTRIES_PER_PAGE-1))
47     #define AVR_ADDR_TO_PAGENR(a) ((a) >> (AVR_IC_ENTRIES_SHIFT \
48     + AVR_INSTR_ALIGNMENT_SHIFT))
49    
50 dpavlin 22 DYNTRANS_MISC_DECLARATIONS(avr,AVR,uint64_t)
51 dpavlin 14
52 dpavlin 22 #define AVR_MAX_VPH_TLB_ENTRIES 128
53 dpavlin 14
54    
55     #define SREG_NAMES "cznvshti"
56    
57     #define AVR_SREG_C 0x01 /* Carry flag */
58     #define AVR_SREG_Z 0x02 /* Zero flag */
59     #define AVR_SREG_N 0x04 /* Negative flag */
60     #define AVR_SREG_V 0x08 /* Overflow flag */
61     #define AVR_SREG_S 0x10 /* Signed test */
62     #define AVR_SREG_H 0x20 /* Half carry flag */
63     #define AVR_SREG_T 0x40 /* Transfer bit */
64     #define AVR_SREG_I 0x80 /* Interrupt enable/disable */
65    
66    
67     struct avr_cpu {
68     uint32_t pc_mask;
69    
70     /*
71     * General Purpose Registers:
72     */
73     uint8_t r[N_AVR_REGS];
74    
75     /* Status register: */
76     uint8_t sreg;
77    
78     /*
79     * In order to keep an accurate cycle count, this variable should be
80     * increased for those instructions that take longer than 1 cycle to
81     * execute. The total number of executed cycles is extra_cycles PLUS
82     * the number of executed instructions.
83     */
84     int64_t extra_cycles;
85    
86    
87     /*
88     * Instruction translation cache:
89     */
90 dpavlin 22 DYNTRANS_ITC(avr)
91 dpavlin 14
92     /*
93 dpavlin 22 * 32-bit virtual -> physical -> host address translation:
94 dpavlin 14 *
95 dpavlin 22 * (All 32 bits are not really needed on AVRs.)
96 dpavlin 14 */
97 dpavlin 22 VPH_TLBS(avr,AVR)
98     VPH32(avr,AVR,uint32_t,uint8_t)
99 dpavlin 14 };
100    
101    
102     /* cpu_avr.c: */
103     void avr_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
104     unsigned char *host_page, int writeflag, uint64_t paddr_page);
105 dpavlin 18 void avr_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
106 dpavlin 14 void avr_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
107     int avr_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
108     unsigned char *data, size_t len, int writeflag, int cache_flags);
109     int avr_cpu_family_init(struct cpu_family *);
110    
111    
112     #endif /* CPU_AVR_H */

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