--- trunk/src/include/cpu_arm.h 2007/10/08 16:19:23 20 +++ trunk/src/include/cpu_arm.h 2007/10/08 16:20:26 28 @@ -2,7 +2,7 @@ #define CPU_ARM_H /* - * Copyright (C) 2005 Anders Gavare. All rights reserved. + * Copyright (C) 2005-2006 Anders Gavare. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -28,7 +28,7 @@ * SUCH DAMAGE. * * - * $Id: cpu_arm.h,v 1.57 2005/11/16 21:15:19 debug Exp $ + * $Id: cpu_arm.h,v 1.68 2006/07/16 13:32:27 debug Exp $ */ #include "misc.h" @@ -69,29 +69,20 @@ "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \ "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" } +#ifdef ONEKPAGE +#define ARM_IC_ENTRIES_SHIFT 8 +#else +#define ARM_IC_ENTRIES_SHIFT 10 +#endif + #define ARM_N_IC_ARGS 3 #define ARM_INSTR_ALIGNMENT_SHIFT 2 -#define ARM_IC_ENTRIES_SHIFT 10 #define ARM_IC_ENTRIES_PER_PAGE (1 << ARM_IC_ENTRIES_SHIFT) #define ARM_PC_TO_IC_ENTRY(a) (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \ & (ARM_IC_ENTRIES_PER_PAGE-1)) #define ARM_ADDR_TO_PAGENR(a) ((a) >> (ARM_IC_ENTRIES_SHIFT \ + ARM_INSTR_ALIGNMENT_SHIFT)) -struct arm_instr_call { - void (*f)(struct cpu *, struct arm_instr_call *); - size_t arg[ARM_N_IC_ARGS]; -}; - -/* Translation cache struct for each physical page: */ -struct arm_tc_physpage { - struct arm_instr_call ics[ARM_IC_ENTRIES_PER_PAGE + 1]; - uint32_t next_ofs; /* or 0 for end of chain */ - uint32_t physaddr; - int flags; -}; - - #define ARM_F_N 8 /* Same as ARM_FLAG_*, but */ #define ARM_F_Z 4 /* for the 'flags' field instead */ #define ARM_F_C 2 /* of cpsr. */ @@ -134,17 +125,9 @@ #define ARM_EXCEPTION_IRQ 6 #define ARM_EXCEPTION_FIQ 7 - -#define ARM_N_VPH_ENTRIES 1048576 +DYNTRANS_MISC_DECLARATIONS(arm,ARM,uint32_t) #define ARM_MAX_VPH_TLB_ENTRIES 128 -struct arm_vpg_tlb_entry { - unsigned char valid; - unsigned char writeflag; - uint32_t vaddr_page; - uint32_t paddr_page; - unsigned char *host_page; -}; struct arm_cpu { @@ -196,18 +179,50 @@ /* * System Control Coprocessor registers: */ - uint32_t control; + uint32_t cachetype; /* Cache Type Register */ + uint32_t control; /* Control Register */ + uint32_t auxctrl; /* Aux. Control Register */ uint32_t ttb; /* Translation Table Base */ uint32_t dacr; /* Domain Access Control */ uint32_t fsr; /* Fault Status Register */ uint32_t far; /* Fault Address Register */ uint32_t pid; /* Process Id Register */ + uint32_t cpar; /* CoProcessor Access Reg. */ + + /* i80321 Coprocessor 6: ICU (Interrupt controller) */ + uint32_t i80321_inten; /* enable */ + uint32_t i80321_isteer; + uint32_t i80321_isrc; /* current assertions */ + uint32_t tmr0; + uint32_t tmr1; + uint32_t tcr0; + uint32_t tcr1; + uint32_t trr0; + uint32_t trr1; + uint32_t tisr; + uint32_t wdtcr; + + /* XScale Coprocessor 14: (Performance Monitoring Unit) */ + /* XSC1 access style: */ + uint32_t xsc1_pmnc; /* Perf. Monitor Ctrl Reg. */ + uint32_t xsc1_ccnt; /* Clock Counter */ + uint32_t xsc1_pmn0; /* Perf. Counter Reg. 0 */ + uint32_t xsc1_pmn1; /* Perf. Counter Reg. 1 */ + /* XSC2 access style: */ + uint32_t xsc2_pmnc; /* Perf. Monitor Ctrl Reg. */ + uint32_t xsc2_ccnt; /* Clock Counter */ + uint32_t xsc2_inten; /* Interrupt Enable */ + uint32_t xsc2_flag; /* Overflow Flag Register */ + uint32_t xsc2_evtsel; /* Event Selection Register */ + uint32_t xsc2_pmn0; /* Perf. Counter Reg. 0 */ + uint32_t xsc2_pmn1; /* Perf. Counter Reg. 1 */ + uint32_t xsc2_pmn2; /* Perf. Counter Reg. 2 */ + uint32_t xsc2_pmn3; /* Perf. Counter Reg. 3 */ /* For caching the host address of the L1 translation table: */ unsigned char *translation_table; uint32_t last_ttb; - /* * Interrupts: */ @@ -215,38 +230,15 @@ /* - * Instruction translation cache: + * Instruction translation cache, and 32-bit virtual -> physical -> + * host address translation: */ - - /* cur_ic_page is a pointer to an array of ARM_IC_ENTRIES_PER_PAGE - instruction call entries. next_ic points to the next such - call to be executed. */ - struct arm_tc_physpage *cur_physpage; - struct arm_instr_call *cur_ic_page; - struct arm_instr_call *next_ic; - - void (*combination_check)(struct cpu *, - struct arm_instr_call *, int low_addr); - - /* - * Virtual -> physical -> host address translation: - * - * host_load and host_store point to arrays of ARM_N_VPH_ENTRIES - * pointers (to host pages); phys_addr points to an array of - * ARM_N_VPH_ENTRIES uint32_t. - */ - - struct arm_vpg_tlb_entry vph_tlb_entry[ARM_MAX_VPH_TLB_ENTRIES]; - unsigned char *host_load[ARM_N_VPH_ENTRIES]; - unsigned char *host_store[ARM_N_VPH_ENTRIES]; - uint32_t phys_addr[ARM_N_VPH_ENTRIES]; - struct arm_tc_physpage *phys_page[ARM_N_VPH_ENTRIES]; - - uint32_t phystranslation[ARM_N_VPH_ENTRIES/32]; - uint8_t vaddr_to_tlbindex[ARM_N_VPH_ENTRIES]; + DYNTRANS_ITC(arm) + VPH_TLBS(arm,ARM) + VPH32(arm,ARM,uint32_t,uint8_t) /* ARM specific: */ - uint32_t is_userpage[ARM_N_VPH_ENTRIES/32]; + uint32_t is_userpage[N_VPH32_ENTRIES/32]; }; @@ -267,6 +259,30 @@ #define ARM_CONTROL_RR 0x4000 #define ARM_CONTROL_L4 0x8000 +/* Auxiliary Control Register bits: */ +#define ARM_AUXCTRL_MD 0x30 /* MiniData Cache Attribute */ +#define ARM_AUXCTRL_MD_SHIFT 4 +#define ARM_AUXCTRL_P 0x02 /* Page Table Memory Attribute */ +#define ARM_AUXCTRL_K 0x01 /* Write Buffer Coalescing Disable */ + +/* Cache Type register bits: */ +#define ARM_CACHETYPE_CLASS 0x1e000000 +#define ARM_CACHETYPE_CLASS_SHIFT 25 +#define ARM_CACHETYPE_HARVARD 0x01000000 +#define ARM_CACHETYPE_HARVARD_SHIFT 24 +#define ARM_CACHETYPE_DSIZE 0x001c0000 +#define ARM_CACHETYPE_DSIZE_SHIFT 18 +#define ARM_CACHETYPE_DASSOC 0x00038000 +#define ARM_CACHETYPE_DASSOC_SHIFT 15 +#define ARM_CACHETYPE_DLINE 0x00003000 +#define ARM_CACHETYPE_DLINE_SHIFT 12 +#define ARM_CACHETYPE_ISIZE 0x000001c0 +#define ARM_CACHETYPE_ISIZE_SHIFT 6 +#define ARM_CACHETYPE_IASSOC 0x00000038 +#define ARM_CACHETYPE_IASSOC_SHIFT 3 +#define ARM_CACHETYPE_ILINE 0x00000003 +#define ARM_CACHETYPE_ILINE_SHIFT 0 + /* cpu_arm.c: */ void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr); void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr, @@ -274,6 +290,7 @@ void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr, uint32_t paddr); void arm_exception(struct cpu *, int); +int arm_run_instr(struct cpu *cpu); void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page); void arm_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); @@ -287,15 +304,15 @@ /* cpu_arm_coproc.c: */ void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd); -void arm_coproc_i80321(struct cpu *cpu, int opcode1, int opcode2, int l_bit, +void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd); -void arm_coproc_i80321_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit, +void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd); /* memory_arm.c: */ -int arm_translate_address(struct cpu *cpu, uint64_t vaddr, +int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags); -int arm_translate_address_mmu(struct cpu *cpu, uint64_t vaddr, +int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags); #endif /* CPU_ARM_H */