--- trunk/src/include/cpu_arm.h	2007/10/08 16:18:31	11
+++ trunk/src/include/cpu_arm.h	2007/10/08 16:18:38	12
@@ -28,7 +28,7 @@
  *  SUCH DAMAGE.
  *
  *
- *  $Id: cpu_arm.h,v 1.10 2005/06/26 22:23:43 debug Exp $
+ *  $Id: cpu_arm.h,v 1.26 2005/08/14 23:44:23 debug Exp $
  */
 
 #include "misc.h"
@@ -44,35 +44,41 @@
 #define	ARM_PC			15
 #define	N_ARM_REGS		16
 
-/*
- *  Translated instruction calls:
- *
- *  The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets
- *  to arm_tc_physpage structs.
- */
-#define	N_IC_ARGS			3
-#define	IC_ENTRIES_SHIFT		10
-#define	IC_ENTRIES_PER_PAGE		(1 << IC_ENTRIES_SHIFT)
-#define	PC_TO_IC_ENTRY(a)		(((a) >> 2) & (IC_ENTRIES_PER_PAGE-1))
-#define	ADDR_TO_PAGENR(a)		((a) >> (IC_ENTRIES_SHIFT+2))
-#define	N_BASE_TABLE_ENTRIES		32768
-#define	PAGENR_TO_TABLE_INDEX(a)	((a) & (N_BASE_TABLE_ENTRIES-1))
-#define	ARM_TRANSLATION_CACHE_SIZE	(1048576 * 16)
-#define	ARM_TRANSLATION_CACHE_MARGIN	65536
+#define	ARM_REG_NAMES		{				\
+	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",		\
+	"r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc"  }
+
+#define	ARM_CONDITION_STRINGS	{				\
+	"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",		\
+	"hi", "ls", "ge", "lt", "gt", "le", "" /*Always*/ , "(INVALID)" }
+
+/*  Names of Data Processing Instructions:  */
+#define	ARM_DPI_NAMES		{				\
+	"and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc",	\
+	"tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }
+
+#define	ARM_N_IC_ARGS			3
+#define	ARM_INSTR_ALIGNMENT_SHIFT	2
+#define	ARM_IC_ENTRIES_SHIFT		10
+#define	ARM_IC_ENTRIES_PER_PAGE		(1 << ARM_IC_ENTRIES_SHIFT)
+#define	ARM_PC_TO_IC_ENTRY(a)		(((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \
+					& (ARM_IC_ENTRIES_PER_PAGE-1))
+#define	ARM_ADDR_TO_PAGENR(a)		((a) >> (ARM_IC_ENTRIES_SHIFT \
+					+ ARM_INSTR_ALIGNMENT_SHIFT))
 
 struct arm_instr_call {
 	void	(*f)(struct cpu *, struct arm_instr_call *);
-	size_t	arg[N_IC_ARGS];
+	size_t	arg[ARM_N_IC_ARGS];
 };
 
+/*  Translation cache struct for each physical page:  */
 struct arm_tc_physpage {
 	uint32_t	next_ofs;	/*  or 0 for end of chain  */
 	uint32_t	physaddr;
 	int		flags;
-	struct arm_instr_call ics[IC_ENTRIES_PER_PAGE + 1];
+	struct arm_instr_call ics[ARM_IC_ENTRIES_PER_PAGE + 1];
 };
 
-#define	ARM_COMBINATIONS		1
 
 #define	ARM_FLAG_N	0x80000000	/*  Negative flag  */
 #define	ARM_FLAG_Z	0x40000000	/*  Zero flag  */
@@ -93,9 +99,27 @@
 #define	ARM_MODE_ABT32	      0x17
 #define	ARM_MODE_UND32	      0x1b
 
+
+#define	ARM_N_VPH_ENTRIES	1048576
+
+#define	ARM_MAX_VPH_TLB_ENTRIES		256
+struct arm_vpg_tlb_entry {
+	int		valid;
+	int		writeflag;
+	int64_t		timestamp;
+	unsigned char	*host_page;
+	uint32_t	vaddr_page;
+	uint32_t	paddr_page;
+};
+
+
 struct arm_cpu {
+	/*
+	 *  Misc.:
+	 */
 	uint32_t		flags;
 
+
 	/*
 	 *  General Purpose Registers (including the program counter):
 	 *
@@ -103,6 +127,7 @@
 	 *  only used to swap to/from when changing modes. (An exception is
 	 *  r[0..7], which are never swapped out, they are always present.)
 	 */
+
 	uint32_t		r[N_ARM_REGS];
 	uint32_t		usr_r8_r14[7];
 	uint32_t		fiq_r8_r14[7];
@@ -111,25 +136,40 @@
 	uint32_t		abt_r13_r14[2];
 	uint32_t		und_r13_r14[2];
 
+
 	/*
 	 *  Instruction translation cache:
 	 */
-	unsigned char		*translation_cache;
-	size_t			translation_cache_cur_ofs;
 
-	/*  cur_ic_page is a pointer to an array of IC_ENTRIES_PER_PAGE
+	/*  cur_ic_page is a pointer to an array of ARM_IC_ENTRIES_PER_PAGE
 	    instruction call entries. next_ic points to the next such
 	    call to be executed.  */
 	struct arm_tc_physpage	*cur_physpage;
 	struct arm_instr_call	*cur_ic_page;
 	struct arm_instr_call	*next_ic;
 
-	int			running_translated;
-	int32_t			n_translated_instrs;
+
+	/*
+	 *  Virtual -> physical -> host address translation:
+	 *
+	 *  host_load and host_store point to arrays of ARM_N_VPH_ENTRIES
+	 *  pointers (to host pages); phys_addr points to an array of
+	 *  ARM_N_VPH_ENTRIES uint32_t.
+	 */
+
+	struct arm_vpg_tlb_entry	vph_tlb_entry[ARM_MAX_VPH_TLB_ENTRIES];
+	unsigned char			*host_load[ARM_N_VPH_ENTRIES];
+	unsigned char			*host_store[ARM_N_VPH_ENTRIES];
+	uint32_t			phys_addr[ARM_N_VPH_ENTRIES];
+	struct arm_tc_physpage		*phys_page[ARM_N_VPH_ENTRIES];
 };
 
 
 /*  cpu_arm.c:  */
+void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
+	unsigned char *host_page, int writeflag, uint64_t paddr_page);
+void arm_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t paddr);
+void arm_invalidate_code_translation_caches(struct cpu *cpu);
 int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
 	unsigned char *data, size_t len, int writeflag, int cache_flags);
 int arm_cpu_family_init(struct cpu_family *);