src/include/cpu_arm.h

#ifndef CPU_ARM_H
#define CPU_ARM_H

/*
 *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_arm.h,v 1.44 2005/10/10 18:43:37 debug Exp $
 */

#include "misc.h"


struct cpu_family;

/*  ARM CPU types:  */
struct arm_cpu_type_def {
        char            *name;
        uint32_t        cpu_id;
        int             flags;
        int             icache_shift;
        int             iway;
        int             dcache_shift;
        int             dway;
};


#define ARM_SL                  10
#define ARM_FP                  11
#define ARM_IP                  12
#define ARM_SP                  13
#define ARM_LR                  14
#define ARM_PC                  15
#define N_ARM_REGS              16

#define ARM_REG_NAMES           {                               \
        "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",         \
        "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc"  }

#define ARM_CONDITION_STRINGS   {                               \
        "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",         \
        "hi", "ls", "ge", "lt", "gt", "le", "" /*Always*/ , "(INVALID)" }

/*  Names of Data Processing Instructions:  */
#define ARM_DPI_NAMES           {                               \
        "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \
        "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }

#define ARM_N_IC_ARGS                   3
#define ARM_INSTR_ALIGNMENT_SHIFT       2
#define ARM_IC_ENTRIES_SHIFT            10
#define ARM_IC_ENTRIES_PER_PAGE         (1 << ARM_IC_ENTRIES_SHIFT)
#define ARM_PC_TO_IC_ENTRY(a)           (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \
                                        & (ARM_IC_ENTRIES_PER_PAGE-1))
#define ARM_ADDR_TO_PAGENR(a)           ((a) >> (ARM_IC_ENTRIES_SHIFT \
                                        + ARM_INSTR_ALIGNMENT_SHIFT))

struct arm_instr_call {
        void    (*f)(struct cpu *, struct arm_instr_call *);
        size_t  arg[ARM_N_IC_ARGS];
};

/*  Translation cache struct for each physical page:  */
struct arm_tc_physpage {
        uint32_t        next_ofs;       /*  or 0 for end of chain  */
        uint32_t        physaddr;
        int             flags;
        struct arm_instr_call ics[ARM_IC_ENTRIES_PER_PAGE + 1];
};


#define ARM_FLAG_N      0x80000000      /*  Negative flag  */
#define ARM_FLAG_Z      0x40000000      /*  Zero flag  */
#define ARM_FLAG_C      0x20000000      /*  Carry flag  */
#define ARM_FLAG_V      0x10000000      /*  Overflow flag  */
#define ARM_FLAG_Q      0x08000000      /*  DSP saturation overflow  */
#define ARM_FLAG_I      0x00000080      /*  Interrupt disable  */
#define ARM_FLAG_F      0x00000040      /*  Fast Interrupt disable  */
#define ARM_FLAG_T      0x00000020      /*  Thumb mode  */

#define ARM_FLAG_MODE   0x0000001f
#define ARM_MODE_USR26        0x00
#define ARM_MODE_FIQ26        0x01
#define ARM_MODE_IRQ26        0x02
#define ARM_MODE_SVC26        0x03
#define ARM_MODE_USR32        0x10
#define ARM_MODE_FIQ32        0x11
#define ARM_MODE_IRQ32        0x12
#define ARM_MODE_SVC32        0x13
#define ARM_MODE_ABT32        0x17
#define ARM_MODE_UND32        0x1b
#define ARM_MODE_SYS32        0x1f

#define ARM_EXCEPTION_TO_MODE   {       \
        ARM_MODE_SVC32, ARM_MODE_UND32, ARM_MODE_SVC32, ARM_MODE_ABT32, \
        ARM_MODE_ABT32, 0,              ARM_MODE_IRQ32, ARM_MODE_FIQ32  }

#define N_ARM_EXCEPTIONS        8

#define ARM_EXCEPTION_RESET     0
#define ARM_EXCEPTION_UND       1
#define ARM_EXCEPTION_SWI       2
#define ARM_EXCEPTION_PREF_ABT  3
#define ARM_EXCEPTION_DATA_ABT  4
/*  5 was address exception in 26-bit ARM  */
#define ARM_EXCEPTION_IRQ       6
#define ARM_EXCEPTION_FIQ       7


#define ARM_N_VPH_ENTRIES       1048576

#define ARM_MAX_VPH_TLB_ENTRIES         32
struct arm_vpg_tlb_entry {
        int             valid;
        int             writeflag;
        int64_t         timestamp;
        unsigned char   *host_page;
        uint32_t        vaddr_page;
        uint32_t        paddr_page;
};


struct arm_cpu {
        /*
         *  Misc.:
         */
        struct arm_cpu_type_def cpu_type;
        uint32_t                of_emul_addr;

        void                    (*coproc[16])(struct cpu *, int opcode1,
                                    int opcode2, int l_bit, int crn, int crm,
                                    int rd);

        /*
         *  General Purpose Registers (including the program counter):
         *
         *  r[] always contains the current register set. The others are
         *  only used to swap to/from when changing modes. (An exception is
         *  r[0..7], which are never swapped out, they are always present.)
         */

        uint32_t                r[N_ARM_REGS];

        uint32_t                default_r8_r14[7];      /*  usr and sys  */
        uint32_t                fiq_r8_r14[7];
        uint32_t                irq_r13_r14[2];
        uint32_t                svc_r13_r14[2];
        uint32_t                abt_r13_r14[2];
        uint32_t                und_r13_r14[2];

        uint32_t                tmp_pc;         /*  Used for load/stores  */

        /*  Flag/status registers:  */
        uint32_t                cpsr;
        uint32_t                spsr_svc;
        uint32_t                spsr_abt;
        uint32_t                spsr_und;
        uint32_t                spsr_irq;
        uint32_t                spsr_fiq;


        /*
         *  System Control Coprocessor registers:
         */
        uint32_t                control;
        uint32_t                ttb;            /*  Translation Table Base  */
        uint32_t                dacr;           /*  Domain Access Control  */
        uint32_t                fsr;            /*  Fault Status Register  */
        uint32_t                far;            /*  Fault Address Register  */
        uint32_t                pid;            /*  Process Id Register  */


        /*
         *  Interrupts:
         */
        int                     irq_asserted;


        /*
         *  Instruction translation cache:
         */

        /*  cur_ic_page is a pointer to an array of ARM_IC_ENTRIES_PER_PAGE
            instruction call entries. next_ic points to the next such
            call to be executed.  */
        struct arm_tc_physpage  *cur_physpage;
        struct arm_instr_call   *cur_ic_page;
        struct arm_instr_call   *next_ic;


        /*
         *  Virtual -> physical -> host address translation:
         *
         *  host_load and host_store point to arrays of ARM_N_VPH_ENTRIES
         *  pointers (to host pages); phys_addr points to an array of
         *  ARM_N_VPH_ENTRIES uint32_t.
         */

        struct arm_vpg_tlb_entry        vph_tlb_entry[ARM_MAX_VPH_TLB_ENTRIES];
        unsigned char                   *host_load[ARM_N_VPH_ENTRIES];
        unsigned char                   *host_store[ARM_N_VPH_ENTRIES];
        uint32_t                        phys_addr[ARM_N_VPH_ENTRIES];
        struct arm_tc_physpage          *phys_page[ARM_N_VPH_ENTRIES];
};


/*  System Control Coprocessor, control bits:  */
#define ARM_CONTROL_MMU         0x0001
#define ARM_CONTROL_ALIGN       0x0002
#define ARM_CONTROL_CACHE       0x0004
#define ARM_CONTROL_WBUFFER     0x0008
#define ARM_CONTROL_PROG32      0x0010
#define ARM_CONTROL_DATA32      0x0020
#define ARM_CONTROL_BIG         0x0080
#define ARM_CONTROL_S           0x0100
#define ARM_CONTROL_R           0x0200
#define ARM_CONTROL_F           0x0400
#define ARM_CONTROL_Z           0x0800
#define ARM_CONTROL_ICACHE      0x1000
#define ARM_CONTROL_V           0x2000
#define ARM_CONTROL_RR          0x4000
#define ARM_CONTROL_L4          0x8000

/*  cpu_arm.c:  */
void arm_exception(struct cpu *, int);
void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void arm_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int);
void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr);
void arm_load_register_bank(struct cpu *cpu);
void arm_save_register_bank(struct cpu *cpu);
int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
        unsigned char *data, size_t len, int writeflag, int cache_flags);
int arm_cpu_family_init(struct cpu_family *);

/*  cpu_arm_coproc.c:  */
void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
        int crn, int crm, int rd);
void arm_coproc_i80321(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
        int crn, int crm, int rd);
void arm_coproc_i80321_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
        int crn, int crm, int rd);

/*  memory_arm.c:  */
int arm_translate_address(struct cpu *cpu, uint64_t vaddr,
        uint64_t *return_addr, int flags);

#endif  /*  CPU_ARM_H  */
1	#ifndef CPU_ARM_H
2	#define CPU_ARM_H
3
4	/*
5	* Copyright (C) 2005 Anders Gavare. All rights reserved.
6	*
7	* Redistribution and use in source and binary forms, with or without
8	* modification, are permitted provided that the following conditions are met:
9	*
10	* 1. Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	* 3. The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28	* SUCH DAMAGE.
29	*
30	*
31	* $Id: cpu_arm.h,v 1.44 2005/10/10 18:43:37 debug Exp $
32	*/
33
34	#include "misc.h"
35
36
37	struct cpu_family;
38
39	/* ARM CPU types: */
40	struct arm_cpu_type_def {
41	char *name;
42	uint32_t cpu_id;
43	int flags;
44	int icache_shift;
45	int iway;
46	int dcache_shift;
47	int dway;
48	};
49
50
51	#define ARM_SL 10
52	#define ARM_FP 11
53	#define ARM_IP 12
54	#define ARM_SP 13
55	#define ARM_LR 14
56	#define ARM_PC 15
57	#define N_ARM_REGS 16
58
59	#define ARM_REG_NAMES { \
60	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
61	"r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }
62
63	#define ARM_CONDITION_STRINGS { \
64	"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", \
65	"hi", "ls", "ge", "lt", "gt", "le", "" /Always/ , "(INVALID)" }
66
67	/* Names of Data Processing Instructions: */
68	#define ARM_DPI_NAMES { \
69	"and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \
70	"tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }
71
72	#define ARM_N_IC_ARGS 3
73	#define ARM_INSTR_ALIGNMENT_SHIFT 2
74	#define ARM_IC_ENTRIES_SHIFT 10
75	#define ARM_IC_ENTRIES_PER_PAGE (1 << ARM_IC_ENTRIES_SHIFT)
76	#define ARM_PC_TO_IC_ENTRY(a) (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \
77	& (ARM_IC_ENTRIES_PER_PAGE-1))
78	#define ARM_ADDR_TO_PAGENR(a) ((a) >> (ARM_IC_ENTRIES_SHIFT \
79	+ ARM_INSTR_ALIGNMENT_SHIFT))
80
81	struct arm_instr_call {
82	void (f)(struct cpu , struct arm_instr_call *);
83	size_t arg[ARM_N_IC_ARGS];
84	};
85
86	/* Translation cache struct for each physical page: */
87	struct arm_tc_physpage {
88	uint32_t next_ofs; /* or 0 for end of chain */
89	uint32_t physaddr;
90	int flags;
91	struct arm_instr_call ics[ARM_IC_ENTRIES_PER_PAGE + 1];
92	};
93
94
95	#define ARM_FLAG_N 0x80000000 /* Negative flag */
96	#define ARM_FLAG_Z 0x40000000 /* Zero flag */
97	#define ARM_FLAG_C 0x20000000 /* Carry flag */
98	#define ARM_FLAG_V 0x10000000 /* Overflow flag */
99	#define ARM_FLAG_Q 0x08000000 /* DSP saturation overflow */
100	#define ARM_FLAG_I 0x00000080 /* Interrupt disable */
101	#define ARM_FLAG_F 0x00000040 /* Fast Interrupt disable */
102	#define ARM_FLAG_T 0x00000020 /* Thumb mode */
103
104	#define ARM_FLAG_MODE 0x0000001f
105	#define ARM_MODE_USR26 0x00
106	#define ARM_MODE_FIQ26 0x01
107	#define ARM_MODE_IRQ26 0x02
108	#define ARM_MODE_SVC26 0x03
109	#define ARM_MODE_USR32 0x10
110	#define ARM_MODE_FIQ32 0x11
111	#define ARM_MODE_IRQ32 0x12
112	#define ARM_MODE_SVC32 0x13
113	#define ARM_MODE_ABT32 0x17
114	#define ARM_MODE_UND32 0x1b
115	#define ARM_MODE_SYS32 0x1f
116
117	#define ARM_EXCEPTION_TO_MODE { \
118	ARM_MODE_SVC32, ARM_MODE_UND32, ARM_MODE_SVC32, ARM_MODE_ABT32, \
119	ARM_MODE_ABT32, 0, ARM_MODE_IRQ32, ARM_MODE_FIQ32 }
120
121	#define N_ARM_EXCEPTIONS 8
122
123	#define ARM_EXCEPTION_RESET 0
124	#define ARM_EXCEPTION_UND 1
125	#define ARM_EXCEPTION_SWI 2
126	#define ARM_EXCEPTION_PREF_ABT 3
127	#define ARM_EXCEPTION_DATA_ABT 4
128	/* 5 was address exception in 26-bit ARM */
129	#define ARM_EXCEPTION_IRQ 6
130	#define ARM_EXCEPTION_FIQ 7
131
132
133	#define ARM_N_VPH_ENTRIES 1048576
134
135	#define ARM_MAX_VPH_TLB_ENTRIES 32
136	struct arm_vpg_tlb_entry {
137	int valid;
138	int writeflag;
139	int64_t timestamp;
140	unsigned char *host_page;
141	uint32_t vaddr_page;
142	uint32_t paddr_page;
143	};
144
145
146	struct arm_cpu {
147	/*
148	* Misc.:
149	*/
150	struct arm_cpu_type_def cpu_type;
151	uint32_t of_emul_addr;
152
153	void (coproc[16])(struct cpu , int opcode1,
154	int opcode2, int l_bit, int crn, int crm,
155	int rd);
156
157	/*
158	* General Purpose Registers (including the program counter):
159	*
160	* r[] always contains the current register set. The others are
161	* only used to swap to/from when changing modes. (An exception is
162	* r[0..7], which are never swapped out, they are always present.)
163	*/
164
165	uint32_t r[N_ARM_REGS];
166
167	uint32_t default_r8_r14[7]; /* usr and sys */
168	uint32_t fiq_r8_r14[7];
169	uint32_t irq_r13_r14[2];
170	uint32_t svc_r13_r14[2];
171	uint32_t abt_r13_r14[2];
172	uint32_t und_r13_r14[2];
173
174	uint32_t tmp_pc; /* Used for load/stores */
175
176	/* Flag/status registers: */
177	uint32_t cpsr;
178	uint32_t spsr_svc;
179	uint32_t spsr_abt;
180	uint32_t spsr_und;
181	uint32_t spsr_irq;
182	uint32_t spsr_fiq;
183
184
185	/*
186	* System Control Coprocessor registers:
187	*/
188	uint32_t control;
189	uint32_t ttb; /* Translation Table Base */
190	uint32_t dacr; /* Domain Access Control */
191	uint32_t fsr; /* Fault Status Register */
192	uint32_t far; /* Fault Address Register */
193	uint32_t pid; /* Process Id Register */
194
195
196	/*
197	* Interrupts:
198	*/
199	int irq_asserted;
200
201
202	/*
203	* Instruction translation cache:
204	*/
205
206	/* cur_ic_page is a pointer to an array of ARM_IC_ENTRIES_PER_PAGE
207	instruction call entries. next_ic points to the next such
208	call to be executed. */
209	struct arm_tc_physpage *cur_physpage;
210	struct arm_instr_call *cur_ic_page;
211	struct arm_instr_call *next_ic;
212
213
214	/*
215	* Virtual -> physical -> host address translation:
216	*
217	* host_load and host_store point to arrays of ARM_N_VPH_ENTRIES
218	* pointers (to host pages); phys_addr points to an array of
219	* ARM_N_VPH_ENTRIES uint32_t.
220	*/
221
222	struct arm_vpg_tlb_entry vph_tlb_entry[ARM_MAX_VPH_TLB_ENTRIES];
223	unsigned char *host_load[ARM_N_VPH_ENTRIES];
224	unsigned char *host_store[ARM_N_VPH_ENTRIES];
225	uint32_t phys_addr[ARM_N_VPH_ENTRIES];
226	struct arm_tc_physpage *phys_page[ARM_N_VPH_ENTRIES];
227	};
228
229
230	/* System Control Coprocessor, control bits: */
231	#define ARM_CONTROL_MMU 0x0001
232	#define ARM_CONTROL_ALIGN 0x0002
233	#define ARM_CONTROL_CACHE 0x0004
234	#define ARM_CONTROL_WBUFFER 0x0008
235	#define ARM_CONTROL_PROG32 0x0010
236	#define ARM_CONTROL_DATA32 0x0020
237	#define ARM_CONTROL_BIG 0x0080
238	#define ARM_CONTROL_S 0x0100
239	#define ARM_CONTROL_R 0x0200
240	#define ARM_CONTROL_F 0x0400
241	#define ARM_CONTROL_Z 0x0800
242	#define ARM_CONTROL_ICACHE 0x1000
243	#define ARM_CONTROL_V 0x2000
244	#define ARM_CONTROL_RR 0x4000
245	#define ARM_CONTROL_L4 0x8000
246
247	/* cpu_arm.c: */
248	void arm_exception(struct cpu *, int);
249	void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
250	unsigned char *host_page, int writeflag, uint64_t paddr_page);
251	void arm_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int);
252	void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
253	void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr);
254	void arm_load_register_bank(struct cpu *cpu);
255	void arm_save_register_bank(struct cpu *cpu);
256	int arm_memory_rw(struct cpu cpu, struct memory mem, uint64_t vaddr,
257	unsigned char *data, size_t len, int writeflag, int cache_flags);
258	int arm_cpu_family_init(struct cpu_family *);
259
260	/* cpu_arm_coproc.c: */
261	void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
262	int crn, int crm, int rd);
263	void arm_coproc_i80321(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
264	int crn, int crm, int rd);
265	void arm_coproc_i80321_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
266	int crn, int crm, int rd);
267
268	/* memory_arm.c: */
269	int arm_translate_address(struct cpu *cpu, uint64_t vaddr,
270	uint64_t *return_addr, int flags);
271
272	#endif /* CPU_ARM_H */