src/include/cpu_arm.h

#ifndef CPU_ARM_H
#define CPU_ARM_H

/*
 *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_arm.h,v 1.66 2006/06/24 21:47:23 debug Exp $
 */

#include "misc.h"


struct cpu_family;

/*  ARM CPU types:  */
struct arm_cpu_type_def {
        char            *name;
        uint32_t        cpu_id;
        int             flags;
        int             icache_shift;
        int             iway;
        int             dcache_shift;
        int             dway;
};


#define ARM_SL                  10
#define ARM_FP                  11
#define ARM_IP                  12
#define ARM_SP                  13
#define ARM_LR                  14
#define ARM_PC                  15
#define N_ARM_REGS              16

#define ARM_REG_NAMES           {                               \
        "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",         \
        "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc"  }

#define ARM_CONDITION_STRINGS   {                               \
        "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",         \
        "hi", "ls", "ge", "lt", "gt", "le", "" /*Always*/ , "(INVALID)" }

/*  Names of Data Processing Instructions:  */
#define ARM_DPI_NAMES           {                               \
        "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \
        "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }

#ifdef ONEKPAGE
#define ARM_IC_ENTRIES_SHIFT            8
#else
#define ARM_IC_ENTRIES_SHIFT            10
#endif

#define ARM_N_IC_ARGS                   3
#define ARM_INSTR_ALIGNMENT_SHIFT       2
#define ARM_IC_ENTRIES_PER_PAGE         (1 << ARM_IC_ENTRIES_SHIFT)
#define ARM_PC_TO_IC_ENTRY(a)           (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \
                                        & (ARM_IC_ENTRIES_PER_PAGE-1))
#define ARM_ADDR_TO_PAGENR(a)           ((a) >> (ARM_IC_ENTRIES_SHIFT \
                                        + ARM_INSTR_ALIGNMENT_SHIFT))

struct arm_instr_call {
        void    (*f)(struct cpu *, struct arm_instr_call *);
        size_t  arg[ARM_N_IC_ARGS];
};

/*  Translation cache struct for each physical page:  */
struct arm_tc_physpage {
        struct arm_instr_call ics[ARM_IC_ENTRIES_PER_PAGE + 1];
        uint32_t        next_ofs;       /*  or 0 for end of chain  */
        uint32_t        physaddr;
        int             flags;
};


#define ARM_F_N         8       /*  Same as ARM_FLAG_*, but        */
#define ARM_F_Z         4       /*  for the 'flags' field instead  */
#define ARM_F_C         2       /*  of cpsr.                       */
#define ARM_F_V         1

#define ARM_FLAG_N      0x80000000      /*  Negative flag  */
#define ARM_FLAG_Z      0x40000000      /*  Zero flag  */
#define ARM_FLAG_C      0x20000000      /*  Carry flag  */
#define ARM_FLAG_V      0x10000000      /*  Overflow flag  */
#define ARM_FLAG_Q      0x08000000      /*  DSP saturation overflow  */
#define ARM_FLAG_I      0x00000080      /*  Interrupt disable  */
#define ARM_FLAG_F      0x00000040      /*  Fast Interrupt disable  */
#define ARM_FLAG_T      0x00000020      /*  Thumb mode  */

#define ARM_FLAG_MODE   0x0000001f
#define ARM_MODE_USR26        0x00
#define ARM_MODE_FIQ26        0x01
#define ARM_MODE_IRQ26        0x02
#define ARM_MODE_SVC26        0x03
#define ARM_MODE_USR32        0x10
#define ARM_MODE_FIQ32        0x11
#define ARM_MODE_IRQ32        0x12
#define ARM_MODE_SVC32        0x13
#define ARM_MODE_ABT32        0x17
#define ARM_MODE_UND32        0x1b
#define ARM_MODE_SYS32        0x1f

#define ARM_EXCEPTION_TO_MODE   {       \
        ARM_MODE_SVC32, ARM_MODE_UND32, ARM_MODE_SVC32, ARM_MODE_ABT32, \
        ARM_MODE_ABT32, 0,              ARM_MODE_IRQ32, ARM_MODE_FIQ32  }

#define N_ARM_EXCEPTIONS        8

#define ARM_EXCEPTION_RESET     0
#define ARM_EXCEPTION_UND       1
#define ARM_EXCEPTION_SWI       2
#define ARM_EXCEPTION_PREF_ABT  3
#define ARM_EXCEPTION_DATA_ABT  4
/*  5 was address exception in 26-bit ARM  */
#define ARM_EXCEPTION_IRQ       6
#define ARM_EXCEPTION_FIQ       7


#define ARM_MAX_VPH_TLB_ENTRIES         128
struct arm_vpg_tlb_entry {
        unsigned char   valid;
        unsigned char   writeflag;
        uint32_t        vaddr_page;
        uint32_t        paddr_page;
        unsigned char   *host_page;
};


struct arm_cpu {
        /*
         *  Misc.:
         */
        struct arm_cpu_type_def cpu_type;
        uint32_t                of_emul_addr;

        void                    (*coproc[16])(struct cpu *, int opcode1,
                                    int opcode2, int l_bit, int crn, int crm,
                                    int rd);

        /*
         *  General Purpose Registers (including the program counter):
         *
         *  r[] always contains the current register set. The others are
         *  only used to swap to/from when changing modes. (An exception is
         *  r[0..7], which are never swapped out, they are always present.)
         */

        uint32_t                r[N_ARM_REGS];

        uint32_t                default_r8_r14[7];      /*  usr and sys  */
        uint32_t                fiq_r8_r14[7];
        uint32_t                irq_r13_r14[2];
        uint32_t                svc_r13_r14[2];
        uint32_t                abt_r13_r14[2];
        uint32_t                und_r13_r14[2];

        uint32_t                tmp_pc;         /*  Used for load/stores  */

        /*
         *  Flag/status registers:
         *
         *  NOTE: 'flags' just contains the 4 flag bits. When cpsr is read,
         *  the flags should be copied from 'flags', and when cpsr is written
         *  to, 'flags' should be updated as well.
         */
        size_t                  flags;
        uint32_t                cpsr;
        uint32_t                spsr_svc;
        uint32_t                spsr_abt;
        uint32_t                spsr_und;
        uint32_t                spsr_irq;
        uint32_t                spsr_fiq;


        /*
         *  System Control Coprocessor registers:
         */
        uint32_t                cachetype;      /*  Cache Type Register  */
        uint32_t                control;        /*  Control Register  */
        uint32_t                auxctrl;        /*  Aux. Control Register  */
        uint32_t                ttb;            /*  Translation Table Base  */
        uint32_t                dacr;           /*  Domain Access Control  */
        uint32_t                fsr;            /*  Fault Status Register  */
        uint32_t                far;            /*  Fault Address Register  */
        uint32_t                pid;            /*  Process Id Register  */
        uint32_t                cpar;           /*  CoProcessor Access Reg.  */

        /*  i80321 Coprocessor 6: ICU (Interrupt controller)  */
        uint32_t                i80321_inten;   /*  enable  */
        uint32_t                i80321_isteer;
        uint32_t                i80321_isrc;    /*  current assertions  */
        uint32_t                tmr0;
        uint32_t                tmr1;
        uint32_t                tcr0;
        uint32_t                tcr1;
        uint32_t                trr0;
        uint32_t                trr1;
        uint32_t                tisr;
        uint32_t                wdtcr;

        /*  XScale Coprocessor 14: (Performance Monitoring Unit)  */
        /*  XSC1 access style:  */
        uint32_t                xsc1_pmnc;      /*  Perf. Monitor Ctrl Reg.  */
        uint32_t                xsc1_ccnt;      /*  Clock Counter  */
        uint32_t                xsc1_pmn0;      /*  Perf. Counter Reg. 0  */
        uint32_t                xsc1_pmn1;      /*  Perf. Counter Reg. 1  */
        /*  XSC2 access style:  */
        uint32_t                xsc2_pmnc;      /*  Perf. Monitor Ctrl Reg.  */
        uint32_t                xsc2_ccnt;      /*  Clock Counter  */
        uint32_t                xsc2_inten;     /*  Interrupt Enable  */
        uint32_t                xsc2_flag;      /*  Overflow Flag Register  */
        uint32_t                xsc2_evtsel;    /*  Event Selection Register  */
        uint32_t                xsc2_pmn0;      /*  Perf. Counter Reg. 0  */
        uint32_t                xsc2_pmn1;      /*  Perf. Counter Reg. 1  */
        uint32_t                xsc2_pmn2;      /*  Perf. Counter Reg. 2  */
        uint32_t                xsc2_pmn3;      /*  Perf. Counter Reg. 3  */

        /*  For caching the host address of the L1 translation table:  */
        unsigned char           *translation_table;
        uint32_t                last_ttb;

        /*
         *  Interrupts:
         */
        int                     irq_asserted;


        /*
         *  Instruction translation cache, and 32-bit virtual -> physical ->
         *  host address translation:
         */
        DYNTRANS_ITC(arm)
        VPH_TLBS(arm,ARM)
        VPH32(arm,ARM,uint32_t,uint8_t)

        /*  ARM specific: */
        uint32_t                        is_userpage[N_VPH32_ENTRIES/32];
};


/*  System Control Coprocessor, control bits:  */
#define ARM_CONTROL_MMU         0x0001
#define ARM_CONTROL_ALIGN       0x0002
#define ARM_CONTROL_CACHE       0x0004
#define ARM_CONTROL_WBUFFER     0x0008
#define ARM_CONTROL_PROG32      0x0010
#define ARM_CONTROL_DATA32      0x0020
#define ARM_CONTROL_BIG         0x0080
#define ARM_CONTROL_S           0x0100
#define ARM_CONTROL_R           0x0200
#define ARM_CONTROL_F           0x0400
#define ARM_CONTROL_Z           0x0800
#define ARM_CONTROL_ICACHE      0x1000
#define ARM_CONTROL_V           0x2000
#define ARM_CONTROL_RR          0x4000
#define ARM_CONTROL_L4          0x8000

/*  Auxiliary Control Register bits:  */
#define ARM_AUXCTRL_MD          0x30    /*  MiniData Cache Attribute  */
#define ARM_AUXCTRL_MD_SHIFT    4
#define ARM_AUXCTRL_P           0x02    /*  Page Table Memory Attribute  */
#define ARM_AUXCTRL_K           0x01    /*  Write Buffer Coalescing Disable  */

/*  Cache Type register bits:  */
#define ARM_CACHETYPE_CLASS             0x1e000000
#define ARM_CACHETYPE_CLASS_SHIFT       25
#define ARM_CACHETYPE_HARVARD           0x01000000
#define ARM_CACHETYPE_HARVARD_SHIFT     24
#define ARM_CACHETYPE_DSIZE             0x001c0000
#define ARM_CACHETYPE_DSIZE_SHIFT       18
#define ARM_CACHETYPE_DASSOC            0x00038000
#define ARM_CACHETYPE_DASSOC_SHIFT      15
#define ARM_CACHETYPE_DLINE             0x00003000
#define ARM_CACHETYPE_DLINE_SHIFT       12
#define ARM_CACHETYPE_ISIZE             0x000001c0
#define ARM_CACHETYPE_ISIZE_SHIFT       6
#define ARM_CACHETYPE_IASSOC            0x00000038
#define ARM_CACHETYPE_IASSOC_SHIFT      3
#define ARM_CACHETYPE_ILINE             0x00000003
#define ARM_CACHETYPE_ILINE_SHIFT       0

/*  cpu_arm.c:  */
void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr);
void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr,
        uint32_t paddr);
void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr,
        uint32_t paddr);
void arm_exception(struct cpu *, int);
void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void arm_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
void arm_load_register_bank(struct cpu *cpu);
void arm_save_register_bank(struct cpu *cpu);
int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
        unsigned char *data, size_t len, int writeflag, int cache_flags);
int arm_cpu_family_init(struct cpu_family *);

/*  cpu_arm_coproc.c:  */
void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
        int crn, int crm, int rd);
void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
        int crn, int crm, int rd);
void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
        int crn, int crm, int rd);

/*  memory_arm.c:  */
int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr,
        uint64_t *return_addr, int flags);
int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr,
        uint64_t *return_addr, int flags);

#endif  /*  CPU_ARM_H  */
1	#ifndef CPU_ARM_H
2	#define CPU_ARM_H
3
4	/*
5	* Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
6	*
7	* Redistribution and use in source and binary forms, with or without
8	* modification, are permitted provided that the following conditions are met:
9	*
10	* 1. Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	* 3. The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28	* SUCH DAMAGE.
29	*
30	*
31	* $Id: cpu_arm.h,v 1.66 2006/06/24 21:47:23 debug Exp $
32	*/
33
34	#include "misc.h"
35
36
37	struct cpu_family;
38
39	/* ARM CPU types: */
40	struct arm_cpu_type_def {
41	char *name;
42	uint32_t cpu_id;
43	int flags;
44	int icache_shift;
45	int iway;
46	int dcache_shift;
47	int dway;
48	};
49
50
51	#define ARM_SL 10
52	#define ARM_FP 11
53	#define ARM_IP 12
54	#define ARM_SP 13
55	#define ARM_LR 14
56	#define ARM_PC 15
57	#define N_ARM_REGS 16
58
59	#define ARM_REG_NAMES { \
60	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
61	"r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }
62
63	#define ARM_CONDITION_STRINGS { \
64	"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", \
65	"hi", "ls", "ge", "lt", "gt", "le", "" /Always/ , "(INVALID)" }
66
67	/* Names of Data Processing Instructions: */
68	#define ARM_DPI_NAMES { \
69	"and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \
70	"tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }
71
72	#ifdef ONEKPAGE
73	#define ARM_IC_ENTRIES_SHIFT 8
74	#else
75	#define ARM_IC_ENTRIES_SHIFT 10
76	#endif
77
78	#define ARM_N_IC_ARGS 3
79	#define ARM_INSTR_ALIGNMENT_SHIFT 2
80	#define ARM_IC_ENTRIES_PER_PAGE (1 << ARM_IC_ENTRIES_SHIFT)
81	#define ARM_PC_TO_IC_ENTRY(a) (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \
82	& (ARM_IC_ENTRIES_PER_PAGE-1))
83	#define ARM_ADDR_TO_PAGENR(a) ((a) >> (ARM_IC_ENTRIES_SHIFT \
84	+ ARM_INSTR_ALIGNMENT_SHIFT))
85
86	struct arm_instr_call {
87	void (f)(struct cpu , struct arm_instr_call *);
88	size_t arg[ARM_N_IC_ARGS];
89	};
90
91	/* Translation cache struct for each physical page: */
92	struct arm_tc_physpage {
93	struct arm_instr_call ics[ARM_IC_ENTRIES_PER_PAGE + 1];
94	uint32_t next_ofs; /* or 0 for end of chain */
95	uint32_t physaddr;
96	int flags;
97	};
98
99
100	#define ARM_F_N 8 /* Same as ARM_FLAG_, but /
101	#define ARM_F_Z 4 /* for the 'flags' field instead */
102	#define ARM_F_C 2 /* of cpsr. */
103	#define ARM_F_V 1
104
105	#define ARM_FLAG_N 0x80000000 /* Negative flag */
106	#define ARM_FLAG_Z 0x40000000 /* Zero flag */
107	#define ARM_FLAG_C 0x20000000 /* Carry flag */
108	#define ARM_FLAG_V 0x10000000 /* Overflow flag */
109	#define ARM_FLAG_Q 0x08000000 /* DSP saturation overflow */
110	#define ARM_FLAG_I 0x00000080 /* Interrupt disable */
111	#define ARM_FLAG_F 0x00000040 /* Fast Interrupt disable */
112	#define ARM_FLAG_T 0x00000020 /* Thumb mode */
113
114	#define ARM_FLAG_MODE 0x0000001f
115	#define ARM_MODE_USR26 0x00
116	#define ARM_MODE_FIQ26 0x01
117	#define ARM_MODE_IRQ26 0x02
118	#define ARM_MODE_SVC26 0x03
119	#define ARM_MODE_USR32 0x10
120	#define ARM_MODE_FIQ32 0x11
121	#define ARM_MODE_IRQ32 0x12
122	#define ARM_MODE_SVC32 0x13
123	#define ARM_MODE_ABT32 0x17
124	#define ARM_MODE_UND32 0x1b
125	#define ARM_MODE_SYS32 0x1f
126
127	#define ARM_EXCEPTION_TO_MODE { \
128	ARM_MODE_SVC32, ARM_MODE_UND32, ARM_MODE_SVC32, ARM_MODE_ABT32, \
129	ARM_MODE_ABT32, 0, ARM_MODE_IRQ32, ARM_MODE_FIQ32 }
130
131	#define N_ARM_EXCEPTIONS 8
132
133	#define ARM_EXCEPTION_RESET 0
134	#define ARM_EXCEPTION_UND 1
135	#define ARM_EXCEPTION_SWI 2
136	#define ARM_EXCEPTION_PREF_ABT 3
137	#define ARM_EXCEPTION_DATA_ABT 4
138	/* 5 was address exception in 26-bit ARM */
139	#define ARM_EXCEPTION_IRQ 6
140	#define ARM_EXCEPTION_FIQ 7
141
142
143	#define ARM_MAX_VPH_TLB_ENTRIES 128
144	struct arm_vpg_tlb_entry {
145	unsigned char valid;
146	unsigned char writeflag;
147	uint32_t vaddr_page;
148	uint32_t paddr_page;
149	unsigned char *host_page;
150	};
151
152
153	struct arm_cpu {
154	/*
155	* Misc.:
156	*/
157	struct arm_cpu_type_def cpu_type;
158	uint32_t of_emul_addr;
159
160	void (coproc[16])(struct cpu , int opcode1,
161	int opcode2, int l_bit, int crn, int crm,
162	int rd);
163
164	/*
165	* General Purpose Registers (including the program counter):
166	*
167	* r[] always contains the current register set. The others are
168	* only used to swap to/from when changing modes. (An exception is
169	* r[0..7], which are never swapped out, they are always present.)
170	*/
171
172	uint32_t r[N_ARM_REGS];
173
174	uint32_t default_r8_r14[7]; /* usr and sys */
175	uint32_t fiq_r8_r14[7];
176	uint32_t irq_r13_r14[2];
177	uint32_t svc_r13_r14[2];
178	uint32_t abt_r13_r14[2];
179	uint32_t und_r13_r14[2];
180
181	uint32_t tmp_pc; /* Used for load/stores */
182
183	/*
184	* Flag/status registers:
185	*
186	* NOTE: 'flags' just contains the 4 flag bits. When cpsr is read,
187	* the flags should be copied from 'flags', and when cpsr is written
188	* to, 'flags' should be updated as well.
189	*/
190	size_t flags;
191	uint32_t cpsr;
192	uint32_t spsr_svc;
193	uint32_t spsr_abt;
194	uint32_t spsr_und;
195	uint32_t spsr_irq;
196	uint32_t spsr_fiq;
197
198
199	/*
200	* System Control Coprocessor registers:
201	*/
202	uint32_t cachetype; /* Cache Type Register */
203	uint32_t control; /* Control Register */
204	uint32_t auxctrl; /* Aux. Control Register */
205	uint32_t ttb; /* Translation Table Base */
206	uint32_t dacr; /* Domain Access Control */
207	uint32_t fsr; /* Fault Status Register */
208	uint32_t far; /* Fault Address Register */
209	uint32_t pid; /* Process Id Register */
210	uint32_t cpar; /* CoProcessor Access Reg. */
211
212	/* i80321 Coprocessor 6: ICU (Interrupt controller) */
213	uint32_t i80321_inten; /* enable */
214	uint32_t i80321_isteer;
215	uint32_t i80321_isrc; /* current assertions */
216	uint32_t tmr0;
217	uint32_t tmr1;
218	uint32_t tcr0;
219	uint32_t tcr1;
220	uint32_t trr0;
221	uint32_t trr1;
222	uint32_t tisr;
223	uint32_t wdtcr;
224
225	/* XScale Coprocessor 14: (Performance Monitoring Unit) */
226	/* XSC1 access style: */
227	uint32_t xsc1_pmnc; /* Perf. Monitor Ctrl Reg. */
228	uint32_t xsc1_ccnt; /* Clock Counter */
229	uint32_t xsc1_pmn0; /* Perf. Counter Reg. 0 */
230	uint32_t xsc1_pmn1; /* Perf. Counter Reg. 1 */
231	/* XSC2 access style: */
232	uint32_t xsc2_pmnc; /* Perf. Monitor Ctrl Reg. */
233	uint32_t xsc2_ccnt; /* Clock Counter */
234	uint32_t xsc2_inten; /* Interrupt Enable */
235	uint32_t xsc2_flag; /* Overflow Flag Register */
236	uint32_t xsc2_evtsel; /* Event Selection Register */
237	uint32_t xsc2_pmn0; /* Perf. Counter Reg. 0 */
238	uint32_t xsc2_pmn1; /* Perf. Counter Reg. 1 */
239	uint32_t xsc2_pmn2; /* Perf. Counter Reg. 2 */
240	uint32_t xsc2_pmn3; /* Perf. Counter Reg. 3 */
241
242	/* For caching the host address of the L1 translation table: */
243	unsigned char *translation_table;
244	uint32_t last_ttb;
245
246	/*
247	* Interrupts:
248	*/
249	int irq_asserted;
250
251
252	/*
253	* Instruction translation cache, and 32-bit virtual -> physical ->
254	* host address translation:
255	*/
256	DYNTRANS_ITC(arm)
257	VPH_TLBS(arm,ARM)
258	VPH32(arm,ARM,uint32_t,uint8_t)
259
260	/* ARM specific: */
261	uint32_t is_userpage[N_VPH32_ENTRIES/32];
262	};
263
264
265	/* System Control Coprocessor, control bits: */
266	#define ARM_CONTROL_MMU 0x0001
267	#define ARM_CONTROL_ALIGN 0x0002
268	#define ARM_CONTROL_CACHE 0x0004
269	#define ARM_CONTROL_WBUFFER 0x0008
270	#define ARM_CONTROL_PROG32 0x0010
271	#define ARM_CONTROL_DATA32 0x0020
272	#define ARM_CONTROL_BIG 0x0080
273	#define ARM_CONTROL_S 0x0100
274	#define ARM_CONTROL_R 0x0200
275	#define ARM_CONTROL_F 0x0400
276	#define ARM_CONTROL_Z 0x0800
277	#define ARM_CONTROL_ICACHE 0x1000
278	#define ARM_CONTROL_V 0x2000
279	#define ARM_CONTROL_RR 0x4000
280	#define ARM_CONTROL_L4 0x8000
281
282	/* Auxiliary Control Register bits: */
283	#define ARM_AUXCTRL_MD 0x30 /* MiniData Cache Attribute */
284	#define ARM_AUXCTRL_MD_SHIFT 4
285	#define ARM_AUXCTRL_P 0x02 /* Page Table Memory Attribute */
286	#define ARM_AUXCTRL_K 0x01 /* Write Buffer Coalescing Disable */
287
288	/* Cache Type register bits: */
289	#define ARM_CACHETYPE_CLASS 0x1e000000
290	#define ARM_CACHETYPE_CLASS_SHIFT 25
291	#define ARM_CACHETYPE_HARVARD 0x01000000
292	#define ARM_CACHETYPE_HARVARD_SHIFT 24
293	#define ARM_CACHETYPE_DSIZE 0x001c0000
294	#define ARM_CACHETYPE_DSIZE_SHIFT 18
295	#define ARM_CACHETYPE_DASSOC 0x00038000
296	#define ARM_CACHETYPE_DASSOC_SHIFT 15
297	#define ARM_CACHETYPE_DLINE 0x00003000
298	#define ARM_CACHETYPE_DLINE_SHIFT 12
299	#define ARM_CACHETYPE_ISIZE 0x000001c0
300	#define ARM_CACHETYPE_ISIZE_SHIFT 6
301	#define ARM_CACHETYPE_IASSOC 0x00000038
302	#define ARM_CACHETYPE_IASSOC_SHIFT 3
303	#define ARM_CACHETYPE_ILINE 0x00000003
304	#define ARM_CACHETYPE_ILINE_SHIFT 0
305
306	/* cpu_arm.c: */
307	void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr);
308	void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr,
309	uint32_t paddr);
310	void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr,
311	uint32_t paddr);
312	void arm_exception(struct cpu *, int);
313	void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
314	unsigned char *host_page, int writeflag, uint64_t paddr_page);
315	void arm_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
316	void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
317	void arm_load_register_bank(struct cpu *cpu);
318	void arm_save_register_bank(struct cpu *cpu);
319	int arm_memory_rw(struct cpu cpu, struct memory mem, uint64_t vaddr,
320	unsigned char *data, size_t len, int writeflag, int cache_flags);
321	int arm_cpu_family_init(struct cpu_family *);
322
323	/* cpu_arm_coproc.c: */
324	void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
325	int crn, int crm, int rd);
326	void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
327	int crn, int crm, int rd);
328	void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
329	int crn, int crm, int rd);
330
331	/* memory_arm.c: */
332	int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr,
333	uint64_t *return_addr, int flags);
334	int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr,
335	uint64_t *return_addr, int flags);
336
337	#endif /* CPU_ARM_H */