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dpavlin |
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#ifndef CPU_ARM_H |
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#define CPU_ARM_H |
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/* |
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* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_arm.h,v 1.75 2007/07/20 09:03:33 debug Exp $ |
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*/ |
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#include "misc.h" |
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#include "interrupt.h" |
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struct cpu_family; |
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/* ARM CPU types: */ |
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struct arm_cpu_type_def { |
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char *name; |
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uint32_t cpu_id; |
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int flags; |
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int icache_shift; |
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int iway; |
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int dcache_shift; |
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int dway; |
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}; |
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#define ARM_SL 10 |
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#define ARM_FP 11 |
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#define ARM_IP 12 |
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#define ARM_SP 13 |
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#define ARM_LR 14 |
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#define ARM_PC 15 |
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#define N_ARM_REGS 16 |
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#define ARM_REG_NAMES { \ |
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ |
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"r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" } |
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#define ARM_CONDITION_STRINGS { \ |
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"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", \ |
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"hi", "ls", "ge", "lt", "gt", "le", "" /*Always*/ , "(INVALID)" } |
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/* Names of Data Processing Instructions: */ |
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#define ARM_DPI_NAMES { \ |
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"and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \ |
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"tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" } |
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#define ARM_IC_ENTRIES_SHIFT 10 |
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#define ARM_N_IC_ARGS 3 |
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#define ARM_INSTR_ALIGNMENT_SHIFT 2 |
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#define ARM_IC_ENTRIES_PER_PAGE (1 << ARM_IC_ENTRIES_SHIFT) |
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#define ARM_PC_TO_IC_ENTRY(a) (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \ |
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& (ARM_IC_ENTRIES_PER_PAGE-1)) |
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#define ARM_ADDR_TO_PAGENR(a) ((a) >> (ARM_IC_ENTRIES_SHIFT \ |
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+ ARM_INSTR_ALIGNMENT_SHIFT)) |
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#define ARM_F_N 8 /* Same as ARM_FLAG_*, but */ |
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#define ARM_F_Z 4 /* for the 'flags' field instead */ |
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#define ARM_F_C 2 /* of cpsr. */ |
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#define ARM_F_V 1 |
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#define ARM_FLAG_N 0x80000000 /* Negative flag */ |
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#define ARM_FLAG_Z 0x40000000 /* Zero flag */ |
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#define ARM_FLAG_C 0x20000000 /* Carry flag */ |
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#define ARM_FLAG_V 0x10000000 /* Overflow flag */ |
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#define ARM_FLAG_Q 0x08000000 /* DSP saturation overflow */ |
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#define ARM_FLAG_I 0x00000080 /* Interrupt disable */ |
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#define ARM_FLAG_F 0x00000040 /* Fast Interrupt disable */ |
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#define ARM_FLAG_T 0x00000020 /* Thumb mode */ |
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#define ARM_FLAG_MODE 0x0000001f |
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#define ARM_MODE_USR26 0x00 |
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#define ARM_MODE_FIQ26 0x01 |
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#define ARM_MODE_IRQ26 0x02 |
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#define ARM_MODE_SVC26 0x03 |
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#define ARM_MODE_USR32 0x10 |
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#define ARM_MODE_FIQ32 0x11 |
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#define ARM_MODE_IRQ32 0x12 |
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#define ARM_MODE_SVC32 0x13 |
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#define ARM_MODE_ABT32 0x17 |
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#define ARM_MODE_UND32 0x1b |
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#define ARM_MODE_SYS32 0x1f |
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#define ARM_EXCEPTION_TO_MODE { \ |
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ARM_MODE_SVC32, ARM_MODE_UND32, ARM_MODE_SVC32, ARM_MODE_ABT32, \ |
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ARM_MODE_ABT32, 0, ARM_MODE_IRQ32, ARM_MODE_FIQ32 } |
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#define N_ARM_EXCEPTIONS 8 |
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#define ARM_EXCEPTION_RESET 0 |
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#define ARM_EXCEPTION_UND 1 |
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#define ARM_EXCEPTION_SWI 2 |
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#define ARM_EXCEPTION_PREF_ABT 3 |
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#define ARM_EXCEPTION_DATA_ABT 4 |
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/* 5 was address exception in 26-bit ARM */ |
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#define ARM_EXCEPTION_IRQ 6 |
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#define ARM_EXCEPTION_FIQ 7 |
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DYNTRANS_MISC_DECLARATIONS(arm,ARM,uint32_t) |
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#define ARM_MAX_VPH_TLB_ENTRIES 384 |
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struct arm_cpu { |
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/* |
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* Misc.: |
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*/ |
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struct arm_cpu_type_def cpu_type; |
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uint32_t of_emul_addr; |
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void (*coproc[16])(struct cpu *, int opcode1, |
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int opcode2, int l_bit, int crn, int crm, |
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int rd); |
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/* |
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* General Purpose Registers (including the program counter): |
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* |
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* r[] always contains the current register set. The others are |
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* only used to swap to/from when changing modes. (An exception is |
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* r[0..7], which are never swapped out, they are always present.) |
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*/ |
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uint32_t r[N_ARM_REGS]; |
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uint32_t default_r8_r14[7]; /* usr and sys */ |
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uint32_t fiq_r8_r14[7]; |
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uint32_t irq_r13_r14[2]; |
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uint32_t svc_r13_r14[2]; |
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uint32_t abt_r13_r14[2]; |
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uint32_t und_r13_r14[2]; |
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uint32_t tmp_pc; /* Used for load/stores */ |
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/* |
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* Flag/status registers: |
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* |
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* NOTE: 'flags' just contains the 4 flag bits. When cpsr is read, |
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* the flags should be copied from 'flags', and when cpsr is written |
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* to, 'flags' should be updated as well. |
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*/ |
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size_t flags; |
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uint32_t cpsr; |
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uint32_t spsr_svc; |
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uint32_t spsr_abt; |
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uint32_t spsr_und; |
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uint32_t spsr_irq; |
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uint32_t spsr_fiq; |
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/* |
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* System Control Coprocessor registers: |
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*/ |
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uint32_t cachetype; /* Cache Type Register */ |
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uint32_t control; /* Control Register */ |
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uint32_t auxctrl; /* Aux. Control Register */ |
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uint32_t ttb; /* Translation Table Base */ |
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uint32_t dacr; /* Domain Access Control */ |
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uint32_t fsr; /* Fault Status Register */ |
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uint32_t far; /* Fault Address Register */ |
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uint32_t pid; /* Process Id Register */ |
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uint32_t cpar; /* CoProcessor Access Reg. */ |
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/* i80321 Coprocessor 6: ICU (Interrupt controller) */ |
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uint32_t i80321_inten; /* enable */ |
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uint32_t i80321_isteer; |
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uint32_t i80321_isrc; /* current assertions */ |
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uint32_t tmr0; |
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uint32_t tmr1; |
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struct interrupt tmr0_irq; |
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struct interrupt tmr1_irq; |
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uint32_t tcr0; |
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uint32_t tcr1; |
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uint32_t trr0; |
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uint32_t trr1; |
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uint32_t tisr; |
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uint32_t wdtcr; |
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/* XScale Coprocessor 14: (Performance Monitoring Unit) */ |
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/* XSC1 access style: */ |
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uint32_t xsc1_pmnc; /* Perf. Monitor Ctrl Reg. */ |
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uint32_t xsc1_ccnt; /* Clock Counter */ |
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uint32_t xsc1_pmn0; /* Perf. Counter Reg. 0 */ |
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uint32_t xsc1_pmn1; /* Perf. Counter Reg. 1 */ |
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/* XSC2 access style: */ |
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uint32_t xsc2_pmnc; /* Perf. Monitor Ctrl Reg. */ |
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uint32_t xsc2_ccnt; /* Clock Counter */ |
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uint32_t xsc2_inten; /* Interrupt Enable */ |
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uint32_t xsc2_flag; /* Overflow Flag Register */ |
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uint32_t xsc2_evtsel; /* Event Selection Register */ |
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uint32_t xsc2_pmn0; /* Perf. Counter Reg. 0 */ |
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uint32_t xsc2_pmn1; /* Perf. Counter Reg. 1 */ |
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uint32_t xsc2_pmn2; /* Perf. Counter Reg. 2 */ |
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uint32_t xsc2_pmn3; /* Perf. Counter Reg. 3 */ |
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/* For caching the host address of the L1 translation table: */ |
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unsigned char *translation_table; |
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uint32_t last_ttb; |
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/* |
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* Interrupts: |
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*/ |
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int irq_asserted; |
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/* |
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* Instruction translation cache, and 32-bit virtual -> physical -> |
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* host address translation: |
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*/ |
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DYNTRANS_ITC(arm) |
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VPH_TLBS(arm,ARM) |
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VPH32_16BITVPHENTRIES(arm,ARM) |
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/* ARM specific: */ |
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dpavlin |
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uint32_t is_userpage[N_VPH32_ENTRIES/32]; |
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}; |
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/* System Control Coprocessor, control bits: */ |
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#define ARM_CONTROL_MMU 0x0001 |
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#define ARM_CONTROL_ALIGN 0x0002 |
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#define ARM_CONTROL_CACHE 0x0004 |
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#define ARM_CONTROL_WBUFFER 0x0008 |
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#define ARM_CONTROL_PROG32 0x0010 |
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#define ARM_CONTROL_DATA32 0x0020 |
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#define ARM_CONTROL_BIG 0x0080 |
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#define ARM_CONTROL_S 0x0100 |
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#define ARM_CONTROL_R 0x0200 |
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#define ARM_CONTROL_F 0x0400 |
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#define ARM_CONTROL_Z 0x0800 |
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#define ARM_CONTROL_ICACHE 0x1000 |
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#define ARM_CONTROL_V 0x2000 |
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#define ARM_CONTROL_RR 0x4000 |
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#define ARM_CONTROL_L4 0x8000 |
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/* Auxiliary Control Register bits: */ |
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#define ARM_AUXCTRL_MD 0x30 /* MiniData Cache Attribute */ |
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#define ARM_AUXCTRL_MD_SHIFT 4 |
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#define ARM_AUXCTRL_P 0x02 /* Page Table Memory Attribute */ |
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#define ARM_AUXCTRL_K 0x01 /* Write Buffer Coalescing Disable */ |
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/* Cache Type register bits: */ |
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#define ARM_CACHETYPE_CLASS 0x1e000000 |
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#define ARM_CACHETYPE_CLASS_SHIFT 25 |
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#define ARM_CACHETYPE_HARVARD 0x01000000 |
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#define ARM_CACHETYPE_HARVARD_SHIFT 24 |
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#define ARM_CACHETYPE_DSIZE 0x001c0000 |
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#define ARM_CACHETYPE_DSIZE_SHIFT 18 |
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#define ARM_CACHETYPE_DASSOC 0x00038000 |
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#define ARM_CACHETYPE_DASSOC_SHIFT 15 |
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#define ARM_CACHETYPE_DLINE 0x00003000 |
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#define ARM_CACHETYPE_DLINE_SHIFT 12 |
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#define ARM_CACHETYPE_ISIZE 0x000001c0 |
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#define ARM_CACHETYPE_ISIZE_SHIFT 6 |
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#define ARM_CACHETYPE_IASSOC 0x00000038 |
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#define ARM_CACHETYPE_IASSOC_SHIFT 3 |
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#define ARM_CACHETYPE_ILINE 0x00000003 |
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#define ARM_CACHETYPE_ILINE_SHIFT 0 |
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dpavlin |
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/* cpu_arm.c: */ |
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void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr); |
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void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr, |
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uint32_t paddr); |
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void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr, |
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uint32_t paddr); |
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dpavlin |
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void arm_exception(struct cpu *, int); |
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int arm_run_instr(struct cpu *cpu); |
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dpavlin |
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void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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dpavlin |
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void arm_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
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dpavlin |
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void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
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void arm_load_register_bank(struct cpu *cpu); |
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void arm_save_register_bank(struct cpu *cpu); |
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dpavlin |
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int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, int writeflag, int cache_flags); |
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int arm_cpu_family_init(struct cpu_family *); |
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/* cpu_arm_coproc.c: */ |
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void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit, |
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int crn, int crm, int rd); |
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dpavlin |
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void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit, |
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dpavlin |
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int crn, int crm, int rd); |
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void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit, |
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dpavlin |
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int crn, int crm, int rd); |
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dpavlin |
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dpavlin |
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/* memory_arm.c: */ |
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dpavlin |
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int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr, |
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dpavlin |
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uint64_t *return_addr, int flags); |
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dpavlin |
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int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr, |
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dpavlin |
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uint64_t *return_addr, int flags); |
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dpavlin |
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dpavlin |
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#endif /* CPU_ARM_H */ |
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