/[gxemul]/trunk/src/include/cpu_arm.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 10 by dpavlin, Mon Oct 8 16:18:27 2007 UTC revision 12 by dpavlin, Mon Oct 8 16:18:38 2007 UTC
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_arm.h,v 1.10 2005/06/26 22:23:43 debug Exp $   *  $Id: cpu_arm.h,v 1.26 2005/08/14 23:44:23 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
# Line 44  struct cpu_family; Line 44  struct cpu_family;
44  #define ARM_PC                  15  #define ARM_PC                  15
45  #define N_ARM_REGS              16  #define N_ARM_REGS              16
46    
47  /*  #define ARM_REG_NAMES           {                               \
48   *  Translated instruction calls:          "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",         \
49   *          "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc"  }
50   *  The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets  
51   *  to arm_tc_physpage structs.  #define ARM_CONDITION_STRINGS   {                               \
52   */          "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",         \
53  #define N_IC_ARGS                       3          "hi", "ls", "ge", "lt", "gt", "le", "" /*Always*/ , "(INVALID)" }
54  #define IC_ENTRIES_SHIFT                10  
55  #define IC_ENTRIES_PER_PAGE             (1 << IC_ENTRIES_SHIFT)  /*  Names of Data Processing Instructions:  */
56  #define PC_TO_IC_ENTRY(a)               (((a) >> 2) & (IC_ENTRIES_PER_PAGE-1))  #define ARM_DPI_NAMES           {                               \
57  #define ADDR_TO_PAGENR(a)               ((a) >> (IC_ENTRIES_SHIFT+2))          "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \
58  #define N_BASE_TABLE_ENTRIES            32768          "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }
59  #define PAGENR_TO_TABLE_INDEX(a)        ((a) & (N_BASE_TABLE_ENTRIES-1))  
60  #define ARM_TRANSLATION_CACHE_SIZE      (1048576 * 16)  #define ARM_N_IC_ARGS                   3
61  #define ARM_TRANSLATION_CACHE_MARGIN    65536  #define ARM_INSTR_ALIGNMENT_SHIFT       2
62    #define ARM_IC_ENTRIES_SHIFT            10
63    #define ARM_IC_ENTRIES_PER_PAGE         (1 << ARM_IC_ENTRIES_SHIFT)
64    #define ARM_PC_TO_IC_ENTRY(a)           (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \
65                                            & (ARM_IC_ENTRIES_PER_PAGE-1))
66    #define ARM_ADDR_TO_PAGENR(a)           ((a) >> (ARM_IC_ENTRIES_SHIFT \
67                                            + ARM_INSTR_ALIGNMENT_SHIFT))
68    
69  struct arm_instr_call {  struct arm_instr_call {
70          void    (*f)(struct cpu *, struct arm_instr_call *);          void    (*f)(struct cpu *, struct arm_instr_call *);
71          size_t  arg[N_IC_ARGS];          size_t  arg[ARM_N_IC_ARGS];
72  };  };
73    
74    /*  Translation cache struct for each physical page:  */
75  struct arm_tc_physpage {  struct arm_tc_physpage {
76          uint32_t        next_ofs;       /*  or 0 for end of chain  */          uint32_t        next_ofs;       /*  or 0 for end of chain  */
77          uint32_t        physaddr;          uint32_t        physaddr;
78          int             flags;          int             flags;
79          struct arm_instr_call ics[IC_ENTRIES_PER_PAGE + 1];          struct arm_instr_call ics[ARM_IC_ENTRIES_PER_PAGE + 1];
80  };  };
81    
 #define ARM_COMBINATIONS                1  
82    
83  #define ARM_FLAG_N      0x80000000      /*  Negative flag  */  #define ARM_FLAG_N      0x80000000      /*  Negative flag  */
84  #define ARM_FLAG_Z      0x40000000      /*  Zero flag  */  #define ARM_FLAG_Z      0x40000000      /*  Zero flag  */
# Line 93  struct arm_tc_physpage { Line 99  struct arm_tc_physpage {
99  #define ARM_MODE_ABT32        0x17  #define ARM_MODE_ABT32        0x17
100  #define ARM_MODE_UND32        0x1b  #define ARM_MODE_UND32        0x1b
101    
102    
103    #define ARM_N_VPH_ENTRIES       1048576
104    
105    #define ARM_MAX_VPH_TLB_ENTRIES         256
106    struct arm_vpg_tlb_entry {
107            int             valid;
108            int             writeflag;
109            int64_t         timestamp;
110            unsigned char   *host_page;
111            uint32_t        vaddr_page;
112            uint32_t        paddr_page;
113    };
114    
115    
116  struct arm_cpu {  struct arm_cpu {
117            /*
118             *  Misc.:
119             */
120          uint32_t                flags;          uint32_t                flags;
121    
122    
123          /*          /*
124           *  General Purpose Registers (including the program counter):           *  General Purpose Registers (including the program counter):
125           *           *
# Line 103  struct arm_cpu { Line 127  struct arm_cpu {
127           *  only used to swap to/from when changing modes. (An exception is           *  only used to swap to/from when changing modes. (An exception is
128           *  r[0..7], which are never swapped out, they are always present.)           *  r[0..7], which are never swapped out, they are always present.)
129           */           */
130    
131          uint32_t                r[N_ARM_REGS];          uint32_t                r[N_ARM_REGS];
132          uint32_t                usr_r8_r14[7];          uint32_t                usr_r8_r14[7];
133          uint32_t                fiq_r8_r14[7];          uint32_t                fiq_r8_r14[7];
# Line 111  struct arm_cpu { Line 136  struct arm_cpu {
136          uint32_t                abt_r13_r14[2];          uint32_t                abt_r13_r14[2];
137          uint32_t                und_r13_r14[2];          uint32_t                und_r13_r14[2];
138    
139    
140          /*          /*
141           *  Instruction translation cache:           *  Instruction translation cache:
142           */           */
         unsigned char           *translation_cache;  
         size_t                  translation_cache_cur_ofs;  
143    
144          /*  cur_ic_page is a pointer to an array of IC_ENTRIES_PER_PAGE          /*  cur_ic_page is a pointer to an array of ARM_IC_ENTRIES_PER_PAGE
145              instruction call entries. next_ic points to the next such              instruction call entries. next_ic points to the next such
146              call to be executed.  */              call to be executed.  */
147          struct arm_tc_physpage  *cur_physpage;          struct arm_tc_physpage  *cur_physpage;
148          struct arm_instr_call   *cur_ic_page;          struct arm_instr_call   *cur_ic_page;
149          struct arm_instr_call   *next_ic;          struct arm_instr_call   *next_ic;
150    
151          int                     running_translated;  
152          int32_t                 n_translated_instrs;          /*
153             *  Virtual -> physical -> host address translation:
154             *
155             *  host_load and host_store point to arrays of ARM_N_VPH_ENTRIES
156             *  pointers (to host pages); phys_addr points to an array of
157             *  ARM_N_VPH_ENTRIES uint32_t.
158             */
159    
160            struct arm_vpg_tlb_entry        vph_tlb_entry[ARM_MAX_VPH_TLB_ENTRIES];
161            unsigned char                   *host_load[ARM_N_VPH_ENTRIES];
162            unsigned char                   *host_store[ARM_N_VPH_ENTRIES];
163            uint32_t                        phys_addr[ARM_N_VPH_ENTRIES];
164            struct arm_tc_physpage          *phys_page[ARM_N_VPH_ENTRIES];
165  };  };
166    
167    
168  /*  cpu_arm.c:  */  /*  cpu_arm.c:  */
169    void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
170            unsigned char *host_page, int writeflag, uint64_t paddr_page);
171    void arm_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t paddr);
172    void arm_invalidate_code_translation_caches(struct cpu *cpu);
173  int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,  int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
174          unsigned char *data, size_t len, int writeflag, int cache_flags);          unsigned char *data, size_t len, int writeflag, int cache_flags);
175  int arm_cpu_family_init(struct cpu_family *);  int arm_cpu_family_init(struct cpu_family *);
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