/[gxemul]/trunk/src/include/cpu_arm.h
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Contents of /trunk/src/include/cpu_arm.h

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Revision 28 - (show annotations)
Mon Oct 8 16:20:26 2007 UTC (12 years ago) by dpavlin
File MIME type: text/plain
File size: 10518 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $
20060626	Continuing on SPARC emulation (beginning on the 'save'
		instruction, register windows, etc).
20060629	Planning statistics gathering (new -s command line option),
		and renaming speed_tricks to allow_instruction_combinations.
20060630	Some minor manual page updates.
		Various cleanups.
		Implementing the -s command line option.
20060701	FINALLY found the bug which prevented Linux and Ultrix from
		running without the ugly hack in the R2000/R3000 cache isol
		code; it was the phystranslation hint array which was buggy.
		Removing the phystranslation hint code completely, for now.
20060702	Minor dyntrans cleanups; invalidation of physpages now only
		invalidate those parts of a page that have actually been
		translated. (32 parts per page.)
		Some MIPS non-R3000 speed fixes.
		Experimenting with MIPS instruction combination for some
		addiu+bne+sw loops, and sw+sw+sw.
		Adding support (again) for larger-than-4KB pages in MIPS tlbw*.
		Continuing on SPARC emulation: adding load/store instructions.
20060704	Fixing a virtual vs physical page shift bug in the new tlbw*
		implementation. Problem noticed by Jakub Jermar. (Many thanks.)
		Moving rfe and eret to cpu_mips_instr.c, since that is the
		only place that uses them nowadays.
20060705	Removing the BSD license from the "testmachine" include files,
		placing them in the public domain instead; this enables the
		testmachine stuff to be used from projects which are
		incompatible with the BSD license for some reason.
20060707	Adding instruction combinations for the R2000/R3000 L1
		I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu,
		various branches followed by addiu or nop, and jr ra followed
		by addiu. The time it takes to perform a full NetBSD/pmax R3000
		install on the laptop has dropped from 573 seconds to 539. :-)
20060708	Adding a framebuffer controller device (dev_fbctrl), which so
		far can be used to change the fb resolution during runtime, but
		in the future will also be useful for accelerated block fill/
		copy, and possibly also simplified character output.
		Adding an instruction combination for NetBSD/pmax' strlen.
20060709	Minor fixes: reading raw files in src/file.c wasn't memblock
		aligned, removing buggy multi_sw MIPS instruction combination,
		etc.
20060711	Adding a machine_qemu.c, which contains a "qemu_mips" machine.
		(It mimics QEMU's MIPS machine mode, so that a test kernel
		made for QEMU_MIPS also can run in GXemul... at least to some
		extent.)  Adding a short section about how to run this mode to
		doc/guestoses.html.
20060714	Misc. minor code cleanups.
20060715	Applying a patch which adds getchar() to promemul/yamon.c
		(from Oleksandr Tymoshenko).
		Adding yamon.h from NetBSD, and rewriting yamon.c to use it
		(instead of ugly hardcoded numbers) + some cleanup.
20060716	Found and fixed the bug which broke single-stepping of 64-bit
		programs between 0.4.0 and 0.4.0.1 (caused by too quick
		refactoring and no testing). Hopefully this fix will not
		break too many other things.
20060718	Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS.
		Re-adding the sw+sw+sw instr comb (the problem was that I had
		ignored endian issues); however, it doesn't seem to give any
		big performance gain.
20060720	Adding a dummy Transputer mode (T414, T800 etc) skeleton (only
		the 'j' and 'ldc' instructions are implemented so far). :-}
20060721	Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus
		misc. other updates to get Linux 2.6 for evbmips/malta working
		(thanks to Alec Voropay for the details).
		FINALLY found and fixed the bug which made tlbw* for non-R3000
		buggy; it was a reference count problem in the dyntrans core.
20060722	Testing stuff; things seem stable enough for a new release.

==============  RELEASE 0.4.1  ==============


1 #ifndef CPU_ARM_H
2 #define CPU_ARM_H
3
4 /*
5 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cpu_arm.h,v 1.68 2006/07/16 13:32:27 debug Exp $
32 */
33
34 #include "misc.h"
35
36
37 struct cpu_family;
38
39 /* ARM CPU types: */
40 struct arm_cpu_type_def {
41 char *name;
42 uint32_t cpu_id;
43 int flags;
44 int icache_shift;
45 int iway;
46 int dcache_shift;
47 int dway;
48 };
49
50
51 #define ARM_SL 10
52 #define ARM_FP 11
53 #define ARM_IP 12
54 #define ARM_SP 13
55 #define ARM_LR 14
56 #define ARM_PC 15
57 #define N_ARM_REGS 16
58
59 #define ARM_REG_NAMES { \
60 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
61 "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }
62
63 #define ARM_CONDITION_STRINGS { \
64 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", \
65 "hi", "ls", "ge", "lt", "gt", "le", "" /*Always*/ , "(INVALID)" }
66
67 /* Names of Data Processing Instructions: */
68 #define ARM_DPI_NAMES { \
69 "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \
70 "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }
71
72 #ifdef ONEKPAGE
73 #define ARM_IC_ENTRIES_SHIFT 8
74 #else
75 #define ARM_IC_ENTRIES_SHIFT 10
76 #endif
77
78 #define ARM_N_IC_ARGS 3
79 #define ARM_INSTR_ALIGNMENT_SHIFT 2
80 #define ARM_IC_ENTRIES_PER_PAGE (1 << ARM_IC_ENTRIES_SHIFT)
81 #define ARM_PC_TO_IC_ENTRY(a) (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \
82 & (ARM_IC_ENTRIES_PER_PAGE-1))
83 #define ARM_ADDR_TO_PAGENR(a) ((a) >> (ARM_IC_ENTRIES_SHIFT \
84 + ARM_INSTR_ALIGNMENT_SHIFT))
85
86 #define ARM_F_N 8 /* Same as ARM_FLAG_*, but */
87 #define ARM_F_Z 4 /* for the 'flags' field instead */
88 #define ARM_F_C 2 /* of cpsr. */
89 #define ARM_F_V 1
90
91 #define ARM_FLAG_N 0x80000000 /* Negative flag */
92 #define ARM_FLAG_Z 0x40000000 /* Zero flag */
93 #define ARM_FLAG_C 0x20000000 /* Carry flag */
94 #define ARM_FLAG_V 0x10000000 /* Overflow flag */
95 #define ARM_FLAG_Q 0x08000000 /* DSP saturation overflow */
96 #define ARM_FLAG_I 0x00000080 /* Interrupt disable */
97 #define ARM_FLAG_F 0x00000040 /* Fast Interrupt disable */
98 #define ARM_FLAG_T 0x00000020 /* Thumb mode */
99
100 #define ARM_FLAG_MODE 0x0000001f
101 #define ARM_MODE_USR26 0x00
102 #define ARM_MODE_FIQ26 0x01
103 #define ARM_MODE_IRQ26 0x02
104 #define ARM_MODE_SVC26 0x03
105 #define ARM_MODE_USR32 0x10
106 #define ARM_MODE_FIQ32 0x11
107 #define ARM_MODE_IRQ32 0x12
108 #define ARM_MODE_SVC32 0x13
109 #define ARM_MODE_ABT32 0x17
110 #define ARM_MODE_UND32 0x1b
111 #define ARM_MODE_SYS32 0x1f
112
113 #define ARM_EXCEPTION_TO_MODE { \
114 ARM_MODE_SVC32, ARM_MODE_UND32, ARM_MODE_SVC32, ARM_MODE_ABT32, \
115 ARM_MODE_ABT32, 0, ARM_MODE_IRQ32, ARM_MODE_FIQ32 }
116
117 #define N_ARM_EXCEPTIONS 8
118
119 #define ARM_EXCEPTION_RESET 0
120 #define ARM_EXCEPTION_UND 1
121 #define ARM_EXCEPTION_SWI 2
122 #define ARM_EXCEPTION_PREF_ABT 3
123 #define ARM_EXCEPTION_DATA_ABT 4
124 /* 5 was address exception in 26-bit ARM */
125 #define ARM_EXCEPTION_IRQ 6
126 #define ARM_EXCEPTION_FIQ 7
127
128 DYNTRANS_MISC_DECLARATIONS(arm,ARM,uint32_t)
129
130 #define ARM_MAX_VPH_TLB_ENTRIES 128
131
132
133 struct arm_cpu {
134 /*
135 * Misc.:
136 */
137 struct arm_cpu_type_def cpu_type;
138 uint32_t of_emul_addr;
139
140 void (*coproc[16])(struct cpu *, int opcode1,
141 int opcode2, int l_bit, int crn, int crm,
142 int rd);
143
144 /*
145 * General Purpose Registers (including the program counter):
146 *
147 * r[] always contains the current register set. The others are
148 * only used to swap to/from when changing modes. (An exception is
149 * r[0..7], which are never swapped out, they are always present.)
150 */
151
152 uint32_t r[N_ARM_REGS];
153
154 uint32_t default_r8_r14[7]; /* usr and sys */
155 uint32_t fiq_r8_r14[7];
156 uint32_t irq_r13_r14[2];
157 uint32_t svc_r13_r14[2];
158 uint32_t abt_r13_r14[2];
159 uint32_t und_r13_r14[2];
160
161 uint32_t tmp_pc; /* Used for load/stores */
162
163 /*
164 * Flag/status registers:
165 *
166 * NOTE: 'flags' just contains the 4 flag bits. When cpsr is read,
167 * the flags should be copied from 'flags', and when cpsr is written
168 * to, 'flags' should be updated as well.
169 */
170 size_t flags;
171 uint32_t cpsr;
172 uint32_t spsr_svc;
173 uint32_t spsr_abt;
174 uint32_t spsr_und;
175 uint32_t spsr_irq;
176 uint32_t spsr_fiq;
177
178
179 /*
180 * System Control Coprocessor registers:
181 */
182 uint32_t cachetype; /* Cache Type Register */
183 uint32_t control; /* Control Register */
184 uint32_t auxctrl; /* Aux. Control Register */
185 uint32_t ttb; /* Translation Table Base */
186 uint32_t dacr; /* Domain Access Control */
187 uint32_t fsr; /* Fault Status Register */
188 uint32_t far; /* Fault Address Register */
189 uint32_t pid; /* Process Id Register */
190 uint32_t cpar; /* CoProcessor Access Reg. */
191
192 /* i80321 Coprocessor 6: ICU (Interrupt controller) */
193 uint32_t i80321_inten; /* enable */
194 uint32_t i80321_isteer;
195 uint32_t i80321_isrc; /* current assertions */
196 uint32_t tmr0;
197 uint32_t tmr1;
198 uint32_t tcr0;
199 uint32_t tcr1;
200 uint32_t trr0;
201 uint32_t trr1;
202 uint32_t tisr;
203 uint32_t wdtcr;
204
205 /* XScale Coprocessor 14: (Performance Monitoring Unit) */
206 /* XSC1 access style: */
207 uint32_t xsc1_pmnc; /* Perf. Monitor Ctrl Reg. */
208 uint32_t xsc1_ccnt; /* Clock Counter */
209 uint32_t xsc1_pmn0; /* Perf. Counter Reg. 0 */
210 uint32_t xsc1_pmn1; /* Perf. Counter Reg. 1 */
211 /* XSC2 access style: */
212 uint32_t xsc2_pmnc; /* Perf. Monitor Ctrl Reg. */
213 uint32_t xsc2_ccnt; /* Clock Counter */
214 uint32_t xsc2_inten; /* Interrupt Enable */
215 uint32_t xsc2_flag; /* Overflow Flag Register */
216 uint32_t xsc2_evtsel; /* Event Selection Register */
217 uint32_t xsc2_pmn0; /* Perf. Counter Reg. 0 */
218 uint32_t xsc2_pmn1; /* Perf. Counter Reg. 1 */
219 uint32_t xsc2_pmn2; /* Perf. Counter Reg. 2 */
220 uint32_t xsc2_pmn3; /* Perf. Counter Reg. 3 */
221
222 /* For caching the host address of the L1 translation table: */
223 unsigned char *translation_table;
224 uint32_t last_ttb;
225
226 /*
227 * Interrupts:
228 */
229 int irq_asserted;
230
231
232 /*
233 * Instruction translation cache, and 32-bit virtual -> physical ->
234 * host address translation:
235 */
236 DYNTRANS_ITC(arm)
237 VPH_TLBS(arm,ARM)
238 VPH32(arm,ARM,uint32_t,uint8_t)
239
240 /* ARM specific: */
241 uint32_t is_userpage[N_VPH32_ENTRIES/32];
242 };
243
244
245 /* System Control Coprocessor, control bits: */
246 #define ARM_CONTROL_MMU 0x0001
247 #define ARM_CONTROL_ALIGN 0x0002
248 #define ARM_CONTROL_CACHE 0x0004
249 #define ARM_CONTROL_WBUFFER 0x0008
250 #define ARM_CONTROL_PROG32 0x0010
251 #define ARM_CONTROL_DATA32 0x0020
252 #define ARM_CONTROL_BIG 0x0080
253 #define ARM_CONTROL_S 0x0100
254 #define ARM_CONTROL_R 0x0200
255 #define ARM_CONTROL_F 0x0400
256 #define ARM_CONTROL_Z 0x0800
257 #define ARM_CONTROL_ICACHE 0x1000
258 #define ARM_CONTROL_V 0x2000
259 #define ARM_CONTROL_RR 0x4000
260 #define ARM_CONTROL_L4 0x8000
261
262 /* Auxiliary Control Register bits: */
263 #define ARM_AUXCTRL_MD 0x30 /* MiniData Cache Attribute */
264 #define ARM_AUXCTRL_MD_SHIFT 4
265 #define ARM_AUXCTRL_P 0x02 /* Page Table Memory Attribute */
266 #define ARM_AUXCTRL_K 0x01 /* Write Buffer Coalescing Disable */
267
268 /* Cache Type register bits: */
269 #define ARM_CACHETYPE_CLASS 0x1e000000
270 #define ARM_CACHETYPE_CLASS_SHIFT 25
271 #define ARM_CACHETYPE_HARVARD 0x01000000
272 #define ARM_CACHETYPE_HARVARD_SHIFT 24
273 #define ARM_CACHETYPE_DSIZE 0x001c0000
274 #define ARM_CACHETYPE_DSIZE_SHIFT 18
275 #define ARM_CACHETYPE_DASSOC 0x00038000
276 #define ARM_CACHETYPE_DASSOC_SHIFT 15
277 #define ARM_CACHETYPE_DLINE 0x00003000
278 #define ARM_CACHETYPE_DLINE_SHIFT 12
279 #define ARM_CACHETYPE_ISIZE 0x000001c0
280 #define ARM_CACHETYPE_ISIZE_SHIFT 6
281 #define ARM_CACHETYPE_IASSOC 0x00000038
282 #define ARM_CACHETYPE_IASSOC_SHIFT 3
283 #define ARM_CACHETYPE_ILINE 0x00000003
284 #define ARM_CACHETYPE_ILINE_SHIFT 0
285
286 /* cpu_arm.c: */
287 void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr);
288 void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr,
289 uint32_t paddr);
290 void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr,
291 uint32_t paddr);
292 void arm_exception(struct cpu *, int);
293 int arm_run_instr(struct cpu *cpu);
294 void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
295 unsigned char *host_page, int writeflag, uint64_t paddr_page);
296 void arm_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
297 void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
298 void arm_load_register_bank(struct cpu *cpu);
299 void arm_save_register_bank(struct cpu *cpu);
300 int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
301 unsigned char *data, size_t len, int writeflag, int cache_flags);
302 int arm_cpu_family_init(struct cpu_family *);
303
304 /* cpu_arm_coproc.c: */
305 void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
306 int crn, int crm, int rd);
307 void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
308 int crn, int crm, int rd);
309 void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
310 int crn, int crm, int rd);
311
312 /* memory_arm.c: */
313 int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr,
314 uint64_t *return_addr, int flags);
315 int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr,
316 uint64_t *return_addr, int flags);
317
318 #endif /* CPU_ARM_H */

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