/[gxemul]/trunk/src/include/cpu_arm.h
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revision 18 by dpavlin, Mon Oct 8 16:19:11 2007 UTC revision 28 by dpavlin, Mon Oct 8 16:20:26 2007 UTC
# Line 2  Line 2 
2  #define CPU_ARM_H  #define CPU_ARM_H
3    
4  /*  /*
5   *  Copyright (C) 2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_arm.h,v 1.53 2005/10/27 14:01:15 debug Exp $   *  $Id: cpu_arm.h,v 1.68 2006/07/16 13:32:27 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
# Line 69  struct arm_cpu_type_def { Line 69  struct arm_cpu_type_def {
69          "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \          "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \
70          "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }          "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }
71    
72    #ifdef ONEKPAGE
73    #define ARM_IC_ENTRIES_SHIFT            8
74    #else
75    #define ARM_IC_ENTRIES_SHIFT            10
76    #endif
77    
78  #define ARM_N_IC_ARGS                   3  #define ARM_N_IC_ARGS                   3
79  #define ARM_INSTR_ALIGNMENT_SHIFT       2  #define ARM_INSTR_ALIGNMENT_SHIFT       2
 #define ARM_IC_ENTRIES_SHIFT            10  
80  #define ARM_IC_ENTRIES_PER_PAGE         (1 << ARM_IC_ENTRIES_SHIFT)  #define ARM_IC_ENTRIES_PER_PAGE         (1 << ARM_IC_ENTRIES_SHIFT)
81  #define ARM_PC_TO_IC_ENTRY(a)           (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \  #define ARM_PC_TO_IC_ENTRY(a)           (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \
82                                          & (ARM_IC_ENTRIES_PER_PAGE-1))                                          & (ARM_IC_ENTRIES_PER_PAGE-1))
83  #define ARM_ADDR_TO_PAGENR(a)           ((a) >> (ARM_IC_ENTRIES_SHIFT \  #define ARM_ADDR_TO_PAGENR(a)           ((a) >> (ARM_IC_ENTRIES_SHIFT \
84                                          + ARM_INSTR_ALIGNMENT_SHIFT))                                          + ARM_INSTR_ALIGNMENT_SHIFT))
85    
86  struct arm_instr_call {  #define ARM_F_N         8       /*  Same as ARM_FLAG_*, but        */
87          void    (*f)(struct cpu *, struct arm_instr_call *);  #define ARM_F_Z         4       /*  for the 'flags' field instead  */
88          size_t  arg[ARM_N_IC_ARGS];  #define ARM_F_C         2       /*  of cpsr.                       */
89  };  #define ARM_F_V         1
   
 /*  Translation cache struct for each physical page:  */  
 struct arm_tc_physpage {  
         struct arm_instr_call ics[ARM_IC_ENTRIES_PER_PAGE + 1];  
         uint32_t        next_ofs;       /*  or 0 for end of chain  */  
         uint32_t        physaddr;  
         int             flags;  
 };  
   
90    
91  #define ARM_FLAG_N      0x80000000      /*  Negative flag  */  #define ARM_FLAG_N      0x80000000      /*  Negative flag  */
92  #define ARM_FLAG_Z      0x40000000      /*  Zero flag  */  #define ARM_FLAG_Z      0x40000000      /*  Zero flag  */
# Line 129  struct arm_tc_physpage { Line 125  struct arm_tc_physpage {
125  #define ARM_EXCEPTION_IRQ       6  #define ARM_EXCEPTION_IRQ       6
126  #define ARM_EXCEPTION_FIQ       7  #define ARM_EXCEPTION_FIQ       7
127    
128    DYNTRANS_MISC_DECLARATIONS(arm,ARM,uint32_t)
 #define ARM_N_VPH_ENTRIES       1048576  
129    
130  #define ARM_MAX_VPH_TLB_ENTRIES         128  #define ARM_MAX_VPH_TLB_ENTRIES         128
 struct arm_vpg_tlb_entry {  
         int             valid;  
         int             writeflag;  
         int64_t         timestamp;  
         unsigned char   *host_page;  
         uint32_t        vaddr_page;  
         uint32_t        paddr_page;  
 };  
131    
132    
133  struct arm_cpu {  struct arm_cpu {
# Line 173  struct arm_cpu { Line 160  struct arm_cpu {
160    
161          uint32_t                tmp_pc;         /*  Used for load/stores  */          uint32_t                tmp_pc;         /*  Used for load/stores  */
162    
163          /*  Flag/status registers:  */          /*
164             *  Flag/status registers:
165             *
166             *  NOTE: 'flags' just contains the 4 flag bits. When cpsr is read,
167             *  the flags should be copied from 'flags', and when cpsr is written
168             *  to, 'flags' should be updated as well.
169             */
170            size_t                  flags;
171          uint32_t                cpsr;          uint32_t                cpsr;
172          uint32_t                spsr_svc;          uint32_t                spsr_svc;
173          uint32_t                spsr_abt;          uint32_t                spsr_abt;
# Line 185  struct arm_cpu { Line 179  struct arm_cpu {
179          /*          /*
180           *  System Control Coprocessor registers:           *  System Control Coprocessor registers:
181           */           */
182          uint32_t                control;          uint32_t                cachetype;      /*  Cache Type Register  */
183            uint32_t                control;        /*  Control Register  */
184            uint32_t                auxctrl;        /*  Aux. Control Register  */
185          uint32_t                ttb;            /*  Translation Table Base  */          uint32_t                ttb;            /*  Translation Table Base  */
186          uint32_t                dacr;           /*  Domain Access Control  */          uint32_t                dacr;           /*  Domain Access Control  */
187          uint32_t                fsr;            /*  Fault Status Register  */          uint32_t                fsr;            /*  Fault Status Register  */
188          uint32_t                far;            /*  Fault Address Register  */          uint32_t                far;            /*  Fault Address Register  */
189          uint32_t                pid;            /*  Process Id Register  */          uint32_t                pid;            /*  Process Id Register  */
190            uint32_t                cpar;           /*  CoProcessor Access Reg.  */
191    
192            /*  i80321 Coprocessor 6: ICU (Interrupt controller)  */
193            uint32_t                i80321_inten;   /*  enable  */
194            uint32_t                i80321_isteer;
195            uint32_t                i80321_isrc;    /*  current assertions  */
196            uint32_t                tmr0;
197            uint32_t                tmr1;
198            uint32_t                tcr0;
199            uint32_t                tcr1;
200            uint32_t                trr0;
201            uint32_t                trr1;
202            uint32_t                tisr;
203            uint32_t                wdtcr;
204    
205            /*  XScale Coprocessor 14: (Performance Monitoring Unit)  */
206            /*  XSC1 access style:  */
207            uint32_t                xsc1_pmnc;      /*  Perf. Monitor Ctrl Reg.  */
208            uint32_t                xsc1_ccnt;      /*  Clock Counter  */
209            uint32_t                xsc1_pmn0;      /*  Perf. Counter Reg. 0  */
210            uint32_t                xsc1_pmn1;      /*  Perf. Counter Reg. 1  */
211            /*  XSC2 access style:  */
212            uint32_t                xsc2_pmnc;      /*  Perf. Monitor Ctrl Reg.  */
213            uint32_t                xsc2_ccnt;      /*  Clock Counter  */
214            uint32_t                xsc2_inten;     /*  Interrupt Enable  */
215            uint32_t                xsc2_flag;      /*  Overflow Flag Register  */
216            uint32_t                xsc2_evtsel;    /*  Event Selection Register  */
217            uint32_t                xsc2_pmn0;      /*  Perf. Counter Reg. 0  */
218            uint32_t                xsc2_pmn1;      /*  Perf. Counter Reg. 1  */
219            uint32_t                xsc2_pmn2;      /*  Perf. Counter Reg. 2  */
220            uint32_t                xsc2_pmn3;      /*  Perf. Counter Reg. 3  */
221    
222          /*  For caching the host address of the L1 translation table:  */          /*  For caching the host address of the L1 translation table:  */
223          unsigned char           *translation_table;          unsigned char           *translation_table;
224          uint32_t                last_ttb;          uint32_t                last_ttb;
225    
   
226          /*          /*
227           *  Interrupts:           *  Interrupts:
228           */           */
# Line 204  struct arm_cpu { Line 230  struct arm_cpu {
230    
231    
232          /*          /*
233           *  Instruction translation cache:           *  Instruction translation cache, and 32-bit virtual -> physical ->
234           */           *  host address translation:
   
         /*  cur_ic_page is a pointer to an array of ARM_IC_ENTRIES_PER_PAGE  
             instruction call entries. next_ic points to the next such  
             call to be executed.  */  
         struct arm_tc_physpage  *cur_physpage;  
         struct arm_instr_call   *cur_ic_page;  
         struct arm_instr_call   *next_ic;  
   
   
         /*  
          *  Virtual -> physical -> host address translation:  
          *  
          *  host_load and host_store point to arrays of ARM_N_VPH_ENTRIES  
          *  pointers (to host pages); phys_addr points to an array of  
          *  ARM_N_VPH_ENTRIES uint32_t.  
235           */           */
236            DYNTRANS_ITC(arm)
237          struct arm_vpg_tlb_entry        vph_tlb_entry[ARM_MAX_VPH_TLB_ENTRIES];          VPH_TLBS(arm,ARM)
238          unsigned char                   *host_load[ARM_N_VPH_ENTRIES];          VPH32(arm,ARM,uint32_t,uint8_t)
         unsigned char                   *host_store[ARM_N_VPH_ENTRIES];  
         uint32_t                        phys_addr[ARM_N_VPH_ENTRIES];  
         struct arm_tc_physpage          *phys_page[ARM_N_VPH_ENTRIES];  
   
         uint32_t                        phystranslation[ARM_N_VPH_ENTRIES/32];  
         int16_t                         vaddr_to_tlbindex[ARM_N_VPH_ENTRIES];  
239    
240          /*  ARM specific: */          /*  ARM specific: */
241          unsigned char                   is_userpage[ARM_N_VPH_ENTRIES/8];          uint32_t                        is_userpage[N_VPH32_ENTRIES/32];
242  };  };
243    
244    
# Line 254  struct arm_cpu { Line 259  struct arm_cpu {
259  #define ARM_CONTROL_RR          0x4000  #define ARM_CONTROL_RR          0x4000
260  #define ARM_CONTROL_L4          0x8000  #define ARM_CONTROL_L4          0x8000
261    
262    /*  Auxiliary Control Register bits:  */
263    #define ARM_AUXCTRL_MD          0x30    /*  MiniData Cache Attribute  */
264    #define ARM_AUXCTRL_MD_SHIFT    4
265    #define ARM_AUXCTRL_P           0x02    /*  Page Table Memory Attribute  */
266    #define ARM_AUXCTRL_K           0x01    /*  Write Buffer Coalescing Disable  */
267    
268    /*  Cache Type register bits:  */
269    #define ARM_CACHETYPE_CLASS             0x1e000000
270    #define ARM_CACHETYPE_CLASS_SHIFT       25
271    #define ARM_CACHETYPE_HARVARD           0x01000000
272    #define ARM_CACHETYPE_HARVARD_SHIFT     24
273    #define ARM_CACHETYPE_DSIZE             0x001c0000
274    #define ARM_CACHETYPE_DSIZE_SHIFT       18
275    #define ARM_CACHETYPE_DASSOC            0x00038000
276    #define ARM_CACHETYPE_DASSOC_SHIFT      15
277    #define ARM_CACHETYPE_DLINE             0x00003000
278    #define ARM_CACHETYPE_DLINE_SHIFT       12
279    #define ARM_CACHETYPE_ISIZE             0x000001c0
280    #define ARM_CACHETYPE_ISIZE_SHIFT       6
281    #define ARM_CACHETYPE_IASSOC            0x00000038
282    #define ARM_CACHETYPE_IASSOC_SHIFT      3
283    #define ARM_CACHETYPE_ILINE             0x00000003
284    #define ARM_CACHETYPE_ILINE_SHIFT       0
285    
286  /*  cpu_arm.c:  */  /*  cpu_arm.c:  */
287  void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr);  void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr);
288  void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr,  void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr,
# Line 261  void arm_translation_table_set_l1(struct Line 290  void arm_translation_table_set_l1(struct
290  void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr,  void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr,
291          uint32_t paddr);          uint32_t paddr);
292  void arm_exception(struct cpu *, int);  void arm_exception(struct cpu *, int);
293    int arm_run_instr(struct cpu *cpu);
294  void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
295          unsigned char *host_page, int writeflag, uint64_t paddr_page);          unsigned char *host_page, int writeflag, uint64_t paddr_page);
296  void arm_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);  void arm_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
# Line 274  int arm_cpu_family_init(struct cpu_famil Line 304  int arm_cpu_family_init(struct cpu_famil
304  /*  cpu_arm_coproc.c:  */  /*  cpu_arm_coproc.c:  */
305  void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,  void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
306          int crn, int crm, int rd);          int crn, int crm, int rd);
307  void arm_coproc_i80321(struct cpu *cpu, int opcode1, int opcode2, int l_bit,  void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
308          int crn, int crm, int rd);          int crn, int crm, int rd);
309  void arm_coproc_i80321_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,  void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
310          int crn, int crm, int rd);          int crn, int crm, int rd);
311    
312  /*  memory_arm.c:  */  /*  memory_arm.c:  */
313  int arm_translate_address(struct cpu *cpu, uint64_t vaddr,  int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr,
314          uint64_t *return_addr, int flags);          uint64_t *return_addr, int flags);
315  int arm_translate_address_mmu(struct cpu *cpu, uint64_t vaddr,  int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr,
316          uint64_t *return_addr, int flags);          uint64_t *return_addr, int flags);
317    
318  #endif  /*  CPU_ARM_H  */  #endif  /*  CPU_ARM_H  */
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